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本文中数字电压表的控制系统采用AT89C51单片机,A/D转换器采用ADC0809为主要硬件,实现数字电压表的硬件电路与软件设计。该系统的数字电压表电路简单,所用的元件较少,成本低,调节工作可实现自动化。还可以方便地进行8路A/D转换量的测量,远程测量结果传送等功能。数字电压表可以测量0~5V的8路输入电压值,并在LCD液晶显示屏上显示出来。 相似文献
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雷达数据协议转换器是空管多雷达处理系统的重要组成部分。它将多路HDLC协议的雷达数据转换成单路IP数据,然后传入多雷达数据处理系统,避免系统为引接多路雷达数据而安装多个HDLC串口卡,较少的接线提高了系统可靠性。该设计提出了一种基于FPGA+STM32的雷达数据协议转换器设计方案,利用FPGA在并行处理方面的优势实现多路HDLC雷达数据的实时采集,FPGA与STM32之间采用串口协议进行通信,由STM32控制W5500以太网芯片完成数据的协议转换。最后,通过实验验证了该设计的可行性和有效性。 相似文献
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介绍了一种基于高性能浮点DSP芯片TMS320C32、CPLD芯片XC95288和A/D采样芯片AD976组成的多路采集系统的工作原理以及设计方法。通过对第一路施加特殊的电压量,在CCS开发环境下读取采样缓冲区的值,并利用Matlab对采样数据进行了全波傅氏变换。此外,该系统已在继电保护中得到广泛应用,实践表明,该系统能较好地解决多路模拟量的采集,并确保了采样数据的安全可靠性。 相似文献
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Mixed analog and digital circuits are realized on a 1.5 μm silicon-gate CMOS chip with +5 V power supply only. The circuit uses CMOS digital gate arrays of 0.32 K to 19.6 K cells and is created without any additional turnaround time or any restriction on the design. Typical internal digital gate (two-input NAND) speed, with a fanout of 3 and a wire length of 3 mm, is 1.4 ns. A voltage comparator with ±8 mV maximum input offset voltage and 60 ns response time, digital-to-analog and analog-to-digital converters with 4-, 6-, and 8-bit resolution, respectively, and an analog switch of 25 Ω on-resistance can be realized on the same chip with digital circuits. Using this technology, about one-tenth of the turnaround time can be achieved compared with full-custom LSIs for the same system. The product development flow and computer-aided-design tools for designing mixed analog and digital gate arrays are the same as for digital gate arrays 相似文献
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一种能解决全电视制式的音视频锁相环设计,在I2C总线控制下与AFC(数字自动频率控制)相配合,完成了视频信号与音频信号的快速捕捉锁定与实时追踪,解决了调谐器需要人为操控完成制式转换的问题。文章详细阐述了完整设计过程,解决了模块级设计、仿真验证与版图设计中的关键技术。该设计的电路模块包括偏置电路及其启动电路、基准电压源、FPLL检波器、压控振荡器、窄带FM-PLL、Nf频率合成器、数字AFC、I2C总线控制器等。并对模拟乘法器、COSTAS环鉴频辅助器、VCO振荡控制范围及低噪设计、窄带PD等功能以及完整系统,采用Spectre仿真器进行了仿真验证。电路设计兼顾双极模拟电路与数字电路的优点,电路结构设计充分考虑了应用兼容性,并在音视频信噪比、锁相精度等多项性能指标上有了很大提高,使用外围简单且操作灵活。 相似文献
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This paper represents the low leakage & the delay performance optimization of Flash type Analog to Digital converter using Augmented Sleep Transistors with Current Mode Logic (ASTCML) at 45 nm technology. It is realized that the leakage power is reduced 50% approximately in ASTCML logic based analog to digital converter design at 1 V supply voltage. Due to reduced leakage power, the probability of causing thermal runaway is decreased and the design stagnation is increased. Even though the featured analog to digital converter is designed using combination of PMOS & NMOS. The anticipated analog to digital converter is appropriate for high speed and wireless network application. In this paper, different consecutive designs with flash type analog to digital converter are represented. 相似文献
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Makie-Fukuda K. Kikuchi T. Matsuura T. Hotta M. 《Solid-State Circuits, IEEE Journal of》1995,30(2):87-92
This paper proposes a method of measuring the influence of digital noise on analog circuits using wide-band voltage comparators as noise detectors. Noise amplitude and r.m.s voltage are successfully measured by this method. A test chip is fabricated to measure the digital noise influence. From the experimental results, it is shown that the digital noise influence can be considerably reduced by using a differential configuration in analog circuits for mixed-signal IC's. The digital noise influence can be further reduced by lowering the digital supply voltage. These results show that the voltage-comparator-based measuring method is effective in measuring the influence of digital noise on analog circuits 相似文献
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ADC外围电路的设计通常包括模拟电路、数字电路和电源电路的设计。为了满足ADC的需要,ADC外围电路的设计重点是输入放大信号,为了使其充分发挥整体性能,必须在ADC转换期间保持输入电压的稳定;为了消除模拟多路开关因阻抗不匹配和转换阶跃信号变化对ADC输入及采样阶段的影响,需在多路开关与ADC之间加接高输入阻抗的电压跟随器,并待阶跃变化稳定后,再让采样保持电路进入采样阶段;为了满足微控制器对时序的要求,必须选择恰当的接口形式。此外,采用良好的接地方式与电压去耦方法,可以避免模拟信号和数字信号受到噪声干扰,也可避免两种信号产生互相干扰。为了防止噪声对数字信号的影响,还使用了相应的隔离方式。 相似文献
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An brief overview is given of the voltage generator system of a 1-Gb synchronous DRAM. The design serves as an example for a state-of-the-art DRAM voltage generator system. A general analysis of the required controlling functionality is derived. A universal and flexible controlling scheme for a voltage generator system is presented, which can easily be modified for future voltage generator design. The main aspect of this controlling scheme is a clear separation between logic (digital) controlling functions and (analog) voltage generating functions. A control path that supplies the various voltage generator blocks with configuration information is introduced. Last, the control path is shown to have an additional advantage of increased testability. Hardware results verifying the concept are presented 相似文献
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Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5% 相似文献