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在密码算法电路中寄存器翻转时刻随机化对芯片抗DPA(differential power analysis)攻击能力有很大影响,因此提出了一种基于寄存器翻转时刻随机化的抗DPA攻击技术,其核心是利用不同频率时钟相位差的变化实现电路中关键寄存器翻转时刻的随机变化.针对跨时钟域的数据和控制信号,提出了需要满足的时序约束条件的计算方法,同时还分析了不同时钟频率对寄存器翻转时刻随机化程度的影响.以AES密码算法协处理器为例,实现了所提出的寄存器翻转时刻随机化技术,通过实验模拟的方法验证了理论分析的正确性.实验结果显示,在合理选择电路工作时钟频率的情况下,所提出的技术能够有效提高密码算法电路的抗DPA攻击性能. 相似文献
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时间维度随机化技术通过插入随机延迟、冗余操作和变频时钟等操作,使得侧信息在时域难以对齐,进而降低了侧信道攻击效率。针对时间维度随机化技术引起的能量迹时域失调的问题,提出了基于趋势序列动态匹配(Trend Series Dynamic Matching, TSDM)的抗时间维度随机化方法,分析了攻击兴趣点的分布,提取了能量迹的趋势信息,刻画了能量迹的形状特征,压缩了能量迹的维度,抑制了噪声的负面影响,实现了数据的动态对齐,进而提高侧信道攻击的效率。面向3种典型时间随机化技术开展方法验证和性能分析,该方法相较多种经典对齐方法在不同噪声环境下的数据对齐效果更好,能量攻击成功率达到100%所需的能量迹数量分别减少了23.8%、24.2%、11.3%。 相似文献
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标量乘法的效率和安全性是椭圆曲线密码体制的瓶颈问题,针对椭圆曲线上标量乘法的实现方法,对普通抗SPA和DPA攻击的标量乘算法进行了研究,并提出一种改进算法。改进算法引入随机变量,将标量进行编码,采用点的底层域快速算法和滑动窗口算法,达到兼顾效率和安全性的目标。当滑动窗口长度为4,标量的二进制位长分别为160、192和224 bit时,改进算法效率分别提高了26.9%,21.5%和27.2%。 相似文献
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随着区块链技术的不断发展,作为区块链技术基石的共识技术受到更多关注,共识技术的发展越发迅速,但依旧存在相关难题。容错类共识算法作为区块链共识技术的代表性之一,依然存在诸多难题待研究,针对容错类共识算法中节点随机性和节点共谋攻击问题进行了研究,提出基于博弈论抗共谋攻击的全局随机化共识算法,通过实现节点的随机化和解决相关安全问题提高区块链网络的安全性和吞吐量。在选择参与容错类共识算法的节点过程中,利用映射函数和加权随机函数实现发起者和验证者节点的全局随机化,从而保证发起者和验证者节点的身份匿名,提高区块链网络的安全性。利用信誉更新模型实现信誉动态更新的同时利用博弈论分析容错类共识算法的安全问题,构造更加正确和高效的算法模型以提高算法的吞吐量并分析发现这类算法中存在超过1/3节点的共谋攻击问题,利用精炼贝叶斯博弈构造共谋合约,分析求得共谋者之间的纳什均衡点,从而解决超过1/3节点的共谋攻击问题。通过安全性分析和实验表明,基于博弈论抗共谋攻击的全局随机化共识算法相对工作量证明(Po W,proof of work)、权益证明(Po S,proof of stake)和实用拜占庭容错(PBFT,... 相似文献
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针对密码算法的高阶DPA攻击方法研究 总被引:1,自引:0,他引:1
差分能量分析(DPA)是一种强大的密码算法攻击技术.一种有效的防御措施是对参与运算的中间数据进行掩码,然而采用掩码技术的密码算法仍然可以用高阶DPA进行攻击.高阶DPA攻击与一般DPA攻击相比较存在很多难点,包括建立正确的攻击模型、选取正确的攻击点、构造适当的组合函数以及提高攻击模型的信噪比等.通过对一种经典的掩码方案进行分析,逐一阐述在高阶DPA攻击中如何解决上述难点,并在硬件实现的算法协处理器上对攻击方法进行了验证. 相似文献
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为提高分组密码算法电路的抗能量攻击能力,参考掩码技术的思想,基于取反的基本操作提出了反向交错的概念,对反向交错的关键性质进行了证明,以此为依据设计了一种反向交错的电路结构,并通过加入一级寄存器的方式打乱时序对齐,得到了优化的电路结构,通过功耗随机化的方法提升了算法的抗能量攻击能力。最后将该结构应用到AES-128算法电路中并进行了加解密功能、防护功能和运算性能三方面的验证,结果表明本文设计的电路结构能正确进行加解密,且具有较好的防护效果和运算性能。 相似文献
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代码注入攻击是应用程序面临的一种主要安全威胁,尤其是Web应用程序,该种攻击源于攻击者能够利用应用程序存在的漏洞/后门,向服务器端注入恶意程序并执行,或者利用应用程序对用户输入的参数缺乏验证和过滤,造成输入作为恶意程序执行,从而达到攻击目的。源程序分析和输入规则匹配等现有防御方法在面对代码注入攻击时都存在着固有缺陷,为了提高Web应用程序对于代码注入攻击的防御性,提出一种基于指令集随机化的抗代码注入方法,该防御方法不依赖于攻击者采用何种攻击方式,能够抵御未知的代码注入攻击。基于该技术及动态、冗余构造方法,设计一套原型系统,采用广义随机Petri网(Generalized Stochastic Petri Net,GSPN)建模计算,攻击者即使在获得随机化方法先验知识的情况下也极难突破系统的防御机制。尽管该方法需要对应用程序源代码进行随机化变换,但处理过程是完全自动化和具有普适性的,通过实验和现网测试表明该方法能够有效抵御大部分代码注入攻击,实现了对攻击的主动防御。 相似文献
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Mask技术破坏了加密过程中的功率消耗与加密的中间变量之间的相关性,提高了加密器件的抗DPA攻击能力。简单地对算法流程添加Mask容易受到高阶DPA攻击的。提出了一种对AES加密过程的各个操作采用多组随机Mask进行屏蔽的方法,并在8bit的MCU上实现了该抗攻击的AES算法。实验结果表明,添加Mask后的抗DPA攻击AES算法能够有效地抵御DPA和高阶DPA的攻击。 相似文献
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《Journal of Microcomputer Applications》1993,16(1):1-17
This paper deals with the RISC design and the first stage evaluation of the UAL processor. UAL stands as Universal Assembly Language. The design and the implementation of the UAL processor will support and speed up the operation of the UAL-E automated environment. UAL-E is used as an environment for the translation and evaluation of assembly programs. The design of the UAL processor is done on a superscalar and pipeline configuration, and the UAL evaluation is based on a set of primitive functions such as procedure call, interrupt service, sorting, search and max, matrixes multiplication, etc. Results from the first stage evaluation of UAL in comparison with other RISC processors are also provided. 相似文献
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C. M. Kalker-Kalkman 《Engineering with Computers》1991,7(3):173-183
Many design problems can be formulated in terms of a number of nonlinear equations and inequalities. A solution of such equations is called a design. In the present paper a method is given for the random generation of a large number of designs, which can be ordered according to some criterion. Using highspeed computer calculation, a large number of random designs is generated from which the designer can make a choice. A trend in selecting certain designs can be imposed: A requirement can be optimized or an optimal compromise between two or more conflicting requirements can be determined. An arbitrary number of variables can be specified. An interactive program has been written and implemented on a number of interactive computer graphics systems. Using the graphic functions, search areas in which the optimum is expected to lie can be modified interactively, thus increasing the speed of convergence. Information about the equations can be given either interactively or in a file, therefore equations can be given either interactively or in a file, therefore relieving the user from the task of programming. The program has been applied to the design of gear pairs, steam condensors, and bearings. 相似文献
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The Monarch architecture team took advantage of custom VLSI in the design of a shared-memory parallel processor. The simple structure eases the task of programming a massively parallel machine 相似文献
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FPGA与通用处理器同步数据传输接口的设计 总被引:1,自引:1,他引:0
针对FPGA与通用处理器之间数据通信的方式,提出了基于包含SDRAM控制器的通用处理器与FPGA实现同步数据传输的方法。该方法通过在FPGA内部构建同步输入/输出接口STI(Synchronous Transmission Interface),将FPGA模拟为包含SDRAM控制器的通用处理器的外接SDRAM存储器,从而实现FPGA与通用处理器之间的同步数据传输。经理论分析和实际电路验证表明,对于FPGA与通用处理器之间的数据通信,在不增加任何硬件成本的前提下,采用该方法较传统异步传输方法传输速率得到显著的提升。 相似文献
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Language processor generators are systems that produce various language processors (including compilers) on the basis of a high-level specification. The design of language processor generators is discussed on the basis of experiments with a traditional compiler writing system (HLP78) employing pore LALR parsing and general attribute grammars. It is argued that these methods are too primitive from the practical point of view. The design of a new language processor generator, HLP84, is based on this view. This system is an attempt to provide high-level tools for a restricted class of applications (one-pass analysis). The syntactic facilities include regular expressions on the right-hand sides of productions, a disambiguating mechanism that is integrated with regular expressions, and a mechanism for using semantic information to aid parsing. The semantic facilities include automatic support for semantic error handling and for symbol tables. Early experiences with the new system show that in spite of the general overhead caused by the higher automation level, the system allows the generation of reasonably efficient processors. 相似文献
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To provide a variety of new and advanced communications services, computer networks are required to perform increasingly complex packet processing. This processing typically takes place on network routers and their associated components. An increasingly central component in router design is a chip-multiprocessor (CMP) referred to as "network processor" or NP. In addition to multiple processors, NPs have multiple forms of on-chip memory, various network and off-chip memory interfaces, and other specialized logic components such as CAMs (content addressable memories). The design space for NPs (e.g., number of processors, caches, cache sizes, etc.) is large due to the diverse workload, application requirements, and system characteristics. System design constraints relate to the maximum chip area and the power consumption that are permissible while achieving defined line rates and executing required packet functions. In this paper, an analytic performance model that captures the processing performance, chip area, and power consumption for a prototypical NP is developed and used to provide quantitative insights into system design trade offs. The model, parameterized with a networking application benchmark, provides the basis for the design of a scalable, high-performance network processor and presents insights into how best to configure the numerous design elements associated with NPs. 相似文献
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随着多种视频编解码标准和视频算法的提出,视频处理器高效性和灵活性显得更为重要。针对视频阵列处理器中数据加载速率与阵列处理单元处理不匹配的问题,通过对视频编解码标准算法的分析,深度挖掘数据访存冗余和传输的特点,在可编程可重构体系结构下,设计了支持灌入和Cache两种工作模式的数据加载电路,并进行了功能仿真和FPGA验证。结果表明,该电路能够满足1080P视频处理对数据加载的要求,采用Desgin Compiler在SMIC 0.13μm CMOS工艺标准单元库下综合,频率可达197 MHz。 相似文献