共查询到17条相似文献,搜索用时 140 毫秒
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研制一种用于无线传感网的多芯片组件(3D-MCM).采用层压、开槽等工艺获得埋置式高密度多层有机(FR-4)基板,通过板上芯片(COB)、板上倒装芯片(FCOB)、球栅阵列(BGA)等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术(SMT)兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成r融合多种互连方式3D-MCM封装结构.埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题.对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性.电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求. 相似文献
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基于埋置式基板的3D-MCM封装结构的研制 总被引:2,自引:0,他引:2
研制一种用于无线传感网的多芯片组件(3D-MCM) . 采用层压、开槽等工艺获得埋置式高密度多层有机(FR-4)基板,通过板上芯片(COB) 、板上倒装芯片(FCOB) 、球栅阵列(BGA)等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术(SMT)兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成了融合多种互连方式3D-MCM封装结构. 埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题. 对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性. 电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求. 相似文献
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叠层三维多芯片组件(3D Multi-Chip Module,MCM)芯片的位置布局直接影响其内部温度场分布,进而影响其可靠性.本文研究了叠层3D-MCM内芯片热布局优化问题,目标是降低芯片最高温度、平均芯片温度场.基于热叠加模型并结合热传导公式,选取芯片的温度作为评价指标,确定出用于3D-MCM热布局优化的适应度函数,采用遗传算法对芯片热布局进行优化,得出了最优芯片热布局方案,总结出了可用于指导叠层3D-MCM芯片热布局设计的热布局规则;采用有限元仿真方法,对所得的热布局优化结果进行验证,结果表明热布局优化结果与仿真实验结果一致,本文所提出的基于热叠加模型的MCM热布局优化算法可实现叠层3D-MCM芯片的热布局优化. 相似文献
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LTCC3D—MCM是采用低温共烧陶瓷(LTCC)为基板,实现有源元件和无源元件高密度集成的组件。垂直互连是完成2D-MCM转化为3D-MCM的重要途径。本文介绍了叠层型LTCC3D—MCM制作的基本工艺和几种垂直互连技术;对垂直互连所形成的焊料凸点、基扳之间的连接进行了分析和讨论。 相似文献
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采用粘塑性有限元焊球模型以及大形变理论研究了三维多芯片组件(3D-MCM)的翘曲形态特征及其成因,结果表明基板腔室的存在使埋置式基板形成了双弓形翘曲形态,焊球的粘塑性使组件在温度循环中出现了翘曲回滞现象.基板中心空腔能改变基板翘曲形态,有利于减小基板翘曲,并有利于提高倒扣焊器件的热机械可靠性.底充胶能够增强3D-MCM的互连强度,并且能够有效降低3D-MCM温度循环后的残留翘曲度.底充胶的热膨胀系数(CTE)过高可能引发3D-MCM新的失效模式.3D-MCM的云纹干涉实验结果与数值分析结果相符较好. 相似文献
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BobChylak IvgWeiQin 《电子工业专用设备》2004,33(3):35-41
叠层管芯封装的不断发展导致该技术能有效地在同一基底内增大电子器件的功能和容量,作为单个芯片。蜂窝电话及其它消费类产品中叠层芯片封装的应用增长促使能够在给定封装尺寸中封装多层芯片。介绍了叠层芯片封装技术中最主要是满足总封装高度的要求。用于叠层芯片封装的技术实现方法包括基片减薄、薄裸芯片贴装、小形貌引线键合、与无支撑的边缘键合以及小偏倒成形等。集中介绍了叠层管芯互连要求。介绍了倒装芯片应用中的正向球形键合、反向球形键合和焊凸凸焊技术,讨论了优点和不足。说明球形键合机的发展能够满足叠层芯片封装的挑战,即超低环形状、长引线跨距和悬空键合等。 相似文献
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H. Oprins A. Srinivasan V. Cherman M. Stucchi P. Marchal E. Cheng 《Microelectronics Journal》2011,42(4):572-578
3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack. 相似文献
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《IEE Review》2004,50(12):40-43
System in package (SiP), as it is being called, is a combination of two or more die stacked together on an interconnection substrate, all within a single package. Typically, there is some sort of processor chip coupled to either memory, a high-performance analogue IC, or to a micro-electro-mechanical system (MEMS) device. A SiP, though, could contain all these elements. This article discusses the challenges faced in SiP technology. 相似文献
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随着电子封装微型化、多功能化的发展,三维封装已成为封装技术的主要发展方向,叠层CSP封装具有封装密度高、互连性能好等特性,是实现三维封装的重要技术。针对超薄芯片传统叠层CSP封装过程中容易产生圆片翘曲、金线键合过程中容易出现0BOP不良、以及线孤(wireloop)的CPK值达不到工艺要求等问题,文中简要介绍了芯片减薄方法对圆片翘曲的影响,利用有限元(FEA)的方法进行芯片减薄后对悬空功能芯片金线键合(Wirebond)的影响进行分析,Filmon Wire(FOW)的贴片(DieAttach)方法在解决悬空功能芯片金线键合中的应用,以及FOW贴片方式对叠层CSP封装流程的简化。采用FOW贴片技术可以达到30%的成本节约,具有很好的经济效益。 相似文献
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We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop-shock tests. 相似文献