A new simple analytical emitter model for bipolar transistors

An accurate analytic evaluation of emitter injection into an arbitrarily doped emitter (including a polysilicon-contacted emitter) is presented taking into account position-dependent quantities such as bandgap narrowing, Auger recombination and mobility. Two newly defined dimensionless parameters are introduced that are very useful for emitter design. These parameters are proposed to replace the conventional emitter Gummel number which becomes less useful when appreciable recombination takes place in the emitter. Universal emitter design curves are presented for devices made in silicon, GaAs and InGaAsP or in any other semiconductor for which a newly introduced lifetime model holds good. Numerical simulations show the accuracy and usefulness of the analytical model developed.     

A new model for bipolar transistors at high current

A model for current gain and cutoff frequency falloff at high currents for bipolar transistors is proposed. The model is based on considering that the vertical and lateral base widening occur simultaneously for a typical bipolar transistor. The results of this model successfully fit Pisces-2B simulation results     

A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors

A comprehensive model-both analytical and numerical-is proposed as a tool to analyze heavily doped emitters of transistors with polycrystalline silicon (polysilicon) contacts. The grains and grain boundaries of polysilicon, the interfacial oxide-like layer between polycrystalline and monocrystalline silicon are lumped respectively into "boxes" in which the drift minority current component is neglected. The mobility reduction of carriers in polysilicon on the whole is explicitly attributed to the additional scattering due to the lattice disorder in the grain boundaries and the carrier tunneling through the interface. The effect of the poly-contacts on transistors can be modeled as a reduced surface recombination velocity for minority carriers in combination with a series emitter resistance for majority carriers. Furthermore, by characterizing the monocrystalline emitter with an effective recombination velocity, the effect of the polysilicon layer on the current gain can be analyzed analytically. Computer simulation is used to verify the assumptions of the model formulation. Using published data [1], the analytical and numerical approaches are compared and it is shown that for these devices a unique combination of physical parameters are needed for the model to fit the data.     

An analytical model for determining carrier transport mechanism of polysilicon emitter bipolar transistors

An analytical model is proposed by including carrier transport mechanisms which previous unified analytical models do not consider: minority carrier combination at both sides of polysilicon-silicon interfacial oxides and thermionic emission over segregation potential barriers for determining the precise carrier transport mechanisms which govern current gain and specific emitter interfacial resistivity. This approach allows us to gain an insight into carrier transport mechanisms and provides a distinct image for polysilicon emitter bipolar devices. With the consideration of the interfacial capture cross section as a function of temperature, the dependence of current gain for devices given an HF etch prior to polysilicon deposition on temperature is first explained successfully. For improving device performance, some directive suggestions are presented.<>     

Extended charge-control model for bipolar transistors

In modeling bipolar transistors the charge-control concept provides a means to predict dynamic behavior from a detailed knowledge of the steady state. As such, it is a first-order approximation lacking accuracy. It is shown that a considerable improvement can be obtained when the concept is extended by allowing time delays in the relations between controlling charges and terminal voltages and currents. It suffices to introduce two delays whose magnitudes can be determined or estimated from the steady-state solution. The increased range of validity of the extended charge-control model is demonstrated in detail, by confronting it with a rigorous model and comparing small-signal parameters.     

一种新的深硅槽工艺技术

提出采用离子注入方法提高主掩膜光刻胶的耐干法腐蚀和腐蚀窗口硅的腐蚀速率,实现了在比较简陋的干法腐蚀设备上采用反应离子腐蚀模式进行深/浅硅槽工艺。     

Compact modeling of thermal resistance in bipolar transistors onbulk and SOI substrates

Analytical expressions for the thermal resistance of bipolar transistors on bulk and SOI substrates are presented. The models are derived on the basis of intuitive physical pictures and validated by comparison with experimental data and three-dimensional (3D) device simulation. The effect of bulk and SOI substrates, shallow- and deep-trench isolation, and multiple emitter fingers is accounted for. All models are suitable for both hand calculations and computer-aided design     

A circuit-compatible analytical device model for ballistic nanowire transistors

Silicon nanowire transistors (SNWTs) have attracted broad attention as a promising device structure for future integrated circuits. Silicon nanowires with a diameter as small as 2 nm and having high carrier mobility have been achieved. Consequently, to develop TCAD tools for SNWT design and to model SNWT for circuit-level simulations have become increasingly important. This paper presents a circuit-compatible closed-form analytical model for ballistic SNWTs. Both the current–voltage (I–V) and capacitance–voltage (C–V) characteristics are modeled in terms of device parameters and terminal voltages. Such a model can be efficiently used in a conventional circuit simulator like SPICE to facilitate transistor-level simulation of large-scale nanowire or mixed nanowire-CMOS circuits and systems.     

Measurement of the base resistance of bipolar transistors

By measuring the transistor parameters hfe and yfb as functions of frequency, it is possible to determine the base resistance of bipolar transistors. This method has proved to be fast and accurate over a relatively large current range for integrated-circuit transistors, as well as for many types of discrete transistors.     

A unified circuit model for bipolar transistors including quasi-saturation effects

This paper describes a compact model for bipolar transistors which includes quasi-saturation effects. The assumptions used in the formulation of this model are clearly stated and justified, and a step by step derivation of the model equations is presented. These equations model both de and charge storage effects. Parameter extraction techniques are qualitatively described and the compact model is evaluated using detailed physical simulations of a high voltage bipolar transistor. In addition, simulations employing this model are compared with measurements and are found to be in excellent agreement.     

A new SIMPLORER model for single-electron transistors

In the first part of this paper, we present simulations of single-electron transistor (SET) output characteristic using Maple. Typical SET I–V characteristics and charge energies curves are presented by developing Maple programs. In the second part of this work, we develop a new model without considering quantum effects using the superposition theorem, transfer function and Laplace transformer. Finally, we propose a new bloc using SIMPLORER 7.0 simulator to modulate quantum effects in the SET island. This model is based on a parallel analog–digital converter.     

A new analytical three-dimensional model for substrate resistance in CMOS latchup structures

A new analytical model based on solving the three-dimensional Laplace equation has been developed to calculate the substrate-spreading resistance of a latchup-sensitive path in internal CMOS structures. This model also provides an analytical closed-form expression for the substrate potential as functions of the structural parameters in the substrate, the dimensions of majority-carrier injector, and the majority-carrier current density across the injector. The calculated results based on the developed model have been compared with existing experimental results, and good agreement has been obtained.     

An analytical model for the epitaxial bipolar transistor

In the n⁺pn^?n⁺ transistor, high-current effects in the base and collector regions are linked within the current ranges of practical interest. To describe such effects, we have derived an analytical model that is based primarily on five assumptions: (1) the structure is approximately one-dimensional; (2) recombination is negligible in the base and collector quasi-neutral regions, and in the three space-charge regions; (3) high-current effects are negligible in the emitter and n⁺-substrate regions; (4) the Fletcher boundary conditions (or the Misawa boundary conditions) can be used for the three space-charge regions; and (5) the ambipolar approach can be used for the base and collector quasi-neutral regions. The primary findings predicted by the n⁺pn^?n⁺ transistor model are: In current ranges of practical interest (usable current gain), the electron concentration profile has a significant “vertical step” located at the collector-base metallurgical junction for all values of collector current. In the limit of extremely-high-current operation, this step tends to vanish. In the current range where the current gain begins to decline rapidly with increasing collector current, the electron concentration at the base boundary of the collector-base space-charge region goes approximately as the square of the hole concentration at the collector boundary of the same region. Because of this relationship, a charge-control calculation is more difficult than a straightforward calculation of carrier concentration for a given degree of accuracy. The n⁺pn^?n⁺ transistor model (which consists of twelve algebraic equations) is particularly useful for the practically important case of an epitaxial bipolar transistor having a very thin, heavily-doped base region.     

Generalized analytical transport modeling of the DC characteristicsof heterojunction bipolar transistors

The current transport mechanisms in double-heterojunction bipolar transistors, including the effects of conduction-band discontinuities of spikes, is analyzed. Two approaches, one based on the back-and-forth motion of electrons in the base between confining spikes and the other on the solution of the continuity equation in the base, are shown to be equivalent. The simplified derivation of the Ebers-Moll-like terminal current expressions ensures that the physical transport mechanisms have not been obscured. The general model is used to match the shape of device DC characteristics successfully by including separately measured parameters and adjusting other unknowns such as injection efficiency. A more complete model is possible by adding effects such as surface and bulk recombination through the emitter injection efficiency term and tunneling through an effective spike height. The physical effects resulting in collector-emitter offset voltages are also fully described and good agreement with experimental results is demonstrated     

A new test structure for extracting extrinsic parameters indouble-polysilicon bipolar transistors

A new test structure for parameter extraction is presented and implemented in a double-polysilicon bipolar junction transistor (BJT) process. The test structure is basically a real BJT, but without the intrinsic base. The test structure allows extraction of the base, collector and emitter impedances, and the extrinsic base-collector capacitance     

A.C. small-signal model for bipolar transistors in saturation

A modified charge-control theory is used to derive a small-signal equivalent circuit which is valid in saturation. From this circuit can be deduced the fT(Ic) and the transconductance gfb(Ie), for example, which are compared with measurements. A short discussion of the results is given.     

A transient model for insulated gate bipolar transistors (IGBTs)

In this paper, we present a physics-based model for the non punch-through (NPT) insulated gate bipolar transistor (IGBT) during transient turn off period. The steady state part of the model is derived from the solution of the ambipolar diffusion equation in the drift region of the NPT IGBT. The transient component of the model is based on the availability of a newly developed expression for the excess carrier concentration in the base. The transient voltage and current are obtained both numerically and analytically from this model. The theoretical predictions of both approaches are compared with experimental data and found to be in good agreement.     

Hot-spot thermal resistance in transistors

By the application of an infrared radiometer as the sensor, hot-spot formation is detected and a hot-spot thermal resistance is calculated. Hot-spot formation for both forward- and reverse-biased second breakdown is analyzed. Pulsed dc techniques are used in the investigation, allowing a wide range of possible operating biases to be applied.     

An analytical model for high electron mobility transistors

In this paper we present a new model for HEMT's which is based on a single analytical function that describes the electron concentrations in the two dimensional electron gas and in the AlGaAs layer. Besides accounting for the AlGaAs conduction, the model includes the effect of mobility degradation, channel length modulation in the saturation region and the series resistances R_S and R_D. The model results in closed form expressions for the current, transconductance, output conductance and gate capacitance. Finally, the theoretical predictions of the model are compared with the experimental data and shown to be in good agreement over a wide range of bias conditions