异质外延碲镉汞薄膜的位错抑制技术

本文简述了MBE异质外延碲镉汞薄膜位错形成机理、位错在外延层中的演化过程以及位错抑制理论,总结了国内外CdTe缓冲层的位错抑制技术、HgCdTe薄膜的位错抑制技术,分析了热循环退火技术各个要素与位错密度变化之间的关系。     

Si基CdTe/HgCdTe分子束外延材料的位错抑制

基于GaAs/Si材料中位错的运动反应理论,修正获得CdTe/Si和HgCdTe/Si外延材料中的位错运动反应模型.采用快速退火方法对Si基HgCdTe外延材料进行位错抑制实验研究,实验结果与理论曲线基本吻合,从理论角度解释了不同高温热处理条件对材料体内位错的抑制作用.对于厚度为4～10μnn的CdTe/Si进行500...     

分子束外延HgCdTe薄膜的CdTe缓冲层特性研究

CdTe是GaAs衬底上分子束外延(MBE)HgCdTe薄膜时的缓冲层,引入缓冲层的目的是减小失配位错,CdTe缓冲层的生长直接影响到后续HgCdTe薄膜的制备质量,然而目前现有文献鲜有报道CdTe缓冲层的最佳厚度.采用X射线双晶衍射、位错腐蚀坑密度(EPD)、FT-IR和椭圆偏振光谱的方法,从CdTe缓冲层厚度对位错密度的影响入手,分析并确定了理想的CdTe缓冲层厚度.     

CdTe/ZnS复合钝化层对长波碲镉汞器件性能的影响研究

采用CdTe/ZnS复合钝化技术对长波HgCdTe薄膜进行表面钝化,并对钝化膜生长工艺进行了改进。采用不同钝化工艺分别制备了MIS器件和二极管器件,并进行了SEM、C-V和I-V表征分析,研究了HgCdTe/钝化层之间的界面特性及其对器件性能的影响。结果表明,钝化工艺改进后所生长的CdTe薄膜更为致密且无大的孔洞,CdTe/HgCdTe界面晶格结构有序度获得改善;采用改进的钝化工艺制备的MIS器件C-V测试曲线呈现高频特性,界面固定电荷面密度从改进前的1.671011 cm-2下降至5.691010 cm-2;采用常规钝化工艺制备的二极管器件在较高反向偏压下出现较大的表面沟道漏电流,新工艺制备的器件表面漏电现象获得了有效抑制。     

不同钝化结构的HgCdTe光伏探测器暗电流机制

在同一HgCdTe晶片上制备了单层ZnS钝化和双层(CdTe+ZnS)钝化的两种光伏探测器,对器件的性能进行了测试,发现双层钝化的器件具有较好的性能.通过理论计算,分析了器件的暗电流机制,发现单层钝化具有较高的表面隧道电流.通过高分辨X射线衍射中的倒易点阵技术研究了单双层钝化对HgCdTe外延层晶格完整性的影响,发现单层ZnS钝化的HgCdTe外延层产生了大量缺陷,而这些缺陷正是单层钝化器件具有较高表面隧道电流的原因.     

Au/CdTe+ZnS/HgCdTe双层介质膜MIS器件的制备及研究

通过介质膜ZnS、CdTe薄膜材料的Ar+束溅射沉积研究,结合HgCdTe器件工艺,成功制备了以ZnS、CdTe双层介质膜为绝缘层的HgCdTeMIS器件;通过对器件的C-V特性实验分析,获得了CdTe/HgCdTe界面电学特性参数.实验表明溅射沉积介质膜CdTe+ZnS对HgCdTe的表面钝化已经可以满足HgCdTe红外焦平面器件表面钝化的各项要求.     

Hg1-xCdxTe光伏探测器的钝化研究

用倒易二维点阵对HgCdTe光伏探测器钝化及其热处理行为进行了研究,发现测射沉积的钝化膜会引起HgCdTe的晶面弯曲,严重的会出现晶面扭曲和mosaic结构,而钝化后的热处理能改善MCT晶体的完整性,在不同的钝化介质层钝化MCT的研究中发现,ZnS钝化层在高温下并不稳定,而CdTe钝化层却能保持较高的耐温性能。     

分子束外延的CdTe在碲镉汞中波器件中钝化效果

采用分子束外延技术（MBE）制备了碲化镉（CdTe）原位钝化的中波碲镉汞（HgCdTe）材料。原子力显微镜（AFM）和扫描电子显微镜（SEM）测试结果表明,分子束原位外延的CdTe可见cross-hatch,表面粗糙度为1～2 nm,CdTe和HgCdTe界面结合紧密。微波光导测试结果显示,77 K时,与表面处理后非原位CdTe钝化的HgCdTe材料相比,CdTe原位钝化的HgCdTe材料的少子寿命较大。制备了分子束外延CdTe原位钝化的中波HgCdTe光伏器件,和相同材料上的非原位CdTe/ZnS双层钝化制备的器件I-V特性相似。     

不同钝化结构的HgCdTe光伏探测器暗电流机制

在同一HgCdTe晶片上制备了单层ZnS钝化和双层（CdTe+ZnS）钝化的两种光伏探测器,对器件的性能进行了测试,发现双层钝化的器件具有较好的性能．通过理论计算,分析了器件的暗电流机制,发现单层钝化具有较高的表面隧道电流．通过高分辨X射线衍射中的倒易点阵技术研究了单双层钝化对HgCdTe外延层晶格完整性的影响,发现单层ZnS钝化的HgCdTe外延层产生了大量缺陷,而这些缺陷正是单层钝化器件具有较高表面隧道电流的原因．     

Au／CdTe＋ZnS／HgCdTe双层介质膜MIS器件的制备及研究

通过介质膜ZnS、CdTe薄膜材料的Ar^ 束溅射沉积研究,结合HgCdTe器件工艺,成功制备了以ZnS、CdTe双层介质膜为绝缘层的HgCdTe MIS器件;通过对器件的C－V特性实验分析,获得了CdTe/HgCdTe界面电学特性参数。实验表明：溅射沉积介质膜CdTe ZnS对HgCdTe的表面钝化已经可以满足HgCdTe红外焦麦面器件表面钝化的各项要求。     

Growth and Analysis of HgCdTe on Alternate Substrates

Dislocations generated at the HgCdTe/CdTe(buffer layer) interface are demonstrated to play a significant role in influencing the crystalline characteristics of HgCdTe epilayers on alternate substrates (AS). A dislocation density >10⁸?cm^?2 is observed at the HgCdTe/CdTe interface. Networks of dislocations are generated at the HgCdTe/CdTe interface. The dislocation networks are observed to entangle. Significant dislocation reduction occurs within a few microns of the HgCdTe/CdTe interface. The reduction in dislocation density as a function of depth is enhanced by annealing. Etch pit density and x-ray diffraction full-width at half-maximum values increase as a function of the lattice mismatch between HgCdTe epilayer and the buffer layer/substrate. The experimental results suggest that only by reducing HgCdTe/CdTe lattice mismatch will the desired crystallinity be achieved for HgCdTe epilayers on AS.     

CdTe/Si复合衬底Ex-situ退火研究

复合衬底CdTe/ZnTe/Si的晶体质量是导致随后外延的HgCdTe外延膜高位错密度的主要原因之一,因此如何提高复合衬底CdTe/Si晶体质量是确保硅基碲镉汞走上工程化的关键所在。降低复合衬底CdTe/Si位错密度方法一般有:生长超晶格缓冲层、衬底偏向、In-situ退火和Ex-situ退火等,本文主要研究Ex-situ退火对复合衬底CdTe/Si晶体质量的影响。研究表明复合衬底经过Ex-situ退火后位错密度最好值达4.2×105cm-2,双晶半峰宽最好值达60arcsec。     

Recent Progress in MBE Growth of CdTe and HgCdTe on (211)B GaAs Substrates

Alternate substrates for molecular beam epitaxy growth of HgCdTe including Si, Ge, and GaAs have been under development for more than a decade. MBE growth of HgCdTe on GaAs substrates was pioneered by Teledyne Imaging Sensors (TIS) in the 1980s. However, recent improvements in the layer crystal quality including improvements in both the CdTe buffer layer and the HgCdTe layer growth have resulted in GaAs emerging as a strong candidate for replacement of bulk CdZnTe substrates for certain infrared imaging applications. In this paper the current state of the art in CdTe and HgCdTe MBE growth on (211)B GaAs and (211) Si at TIS is reviewed. Recent improvements in the CdTe buffer layer quality (double crystal rocking curve full-width at half-maximum?≈?30?arcsec) with HgCdTe dislocation densities of ≤10⁶?cm^?2 are discussed and comparisons are made with historical HgCdTe on bulk CdZnTe and alternate substrate data at TIS. Material properties including the HgCdTe majority carrier mobility and dislocation density are presented as a function of the CdTe buffer layer quality.     

Dislocation profiles in HgCdTe(100) on GaAs(100) grown by metalorganic chemical vapor deposition

We studied dislocation etch pit density (EPD) profiles in HgCdTe(lOO) layers grown on GaAs(lOO) by metalorganic chemical vapor deposition. Dislocation profiles in HgCdTe(lll)B and HgCdTe(lOO) layers differ as follows: Misfit dislocations in HgCdTe(lll)B layers are concentrated near the HgCdTe/CdTe interfaces because of slip planes parallel to the interfaces. Away from the HgCdTe/CdTe interface, the HgCdTe(111)B dislocation density remains almost constant. In HgCdTe(lOO) layers, however, the dislocations propagate monotonically to the surface and the dislocation density decreases gradually as dislocations are incorporated with increasing HgCdTe(lOO) layer thicknesses. The dislocation reduction was small in HgCdTe(lOO) layers more than 10 μm from the HgCdTe/CdTe interface. The CdTe(lOO) buffer thickness and dislocation density were similarly related. Since dislocations glide to accommodate the lattice distortion and this movement increases the probability of dislocation incorporation, incorporation proceeds in limited regions from each interface where the lattice distortion and strain are sufficient. We obtained the minimum EPD in HgCdTe(100) of 1 to 3 x 10⁶ cm^-2 by growing both the epitaxial layers more than 8 μm thick.     

Passivation of HgCdTe p-n diode junction by compositionally graded HgCdTe formed by annealing in a Cd/Hg atmosphere

Cadmium telluride (CdTe) is being widely used for passivating the HgCdTe p-n diode junction. Instead of CdTe, we tried a compositionally graded HgCdTe as a passivation layer that was formed by annealing an HgCdTe p-n junction in a Cd/Hg atmosphere. During annealing, Cd diffuses into HgCdTe from the Cd vapor, while Hg diffuses out from HgCdTe, forming compositionally graded HgCdTe at the surface. The Cd mole fraction at the surface was constant regardless of the annealing temperature in the range of 250–350°C. Capacitance versus voltage (C-V) curves for p-type HgCdTe that were passivated with compositionally graded HgCdTe formed by Cd/Hg annealing at 260°C showed a smaller flat-band voltage than the one passivated by thermally deposited CdTe, indicative of the better quality of the passivation. A long-wave infrared (LWIR) HgCdTe p-n junction diode passivated by compositionally graded HgCdTe showed about a one order of magnitude smaller R_dA value than the one passivated by thermally deposited CdTe, confirming the effectiveness of the compositionally graded HgCdTe as a passivant.     

Impurity Gettering in (112)B HgCdTe/CdTe/Alternate Substrates

The crystalline structure and impurity profiles of HgCdTe/CdTe/alternate substrate (AS; Si and GaAs are possibilities) and CdTe/AS were analyzed by secondary-ion mass spectrometry, atomic force microscopy, etch pit density analysis, and scanning transmission electron microscopy. Impurities (Li, Na, and K) were shown to getter in as-grown CdTe/Si epilayers at in situ Te-stabilized thermal anneal (~500°C) interfaces. In HgCdTe/CdTe/Si epilayers, indium accumulation was observed at Te-stabilized thermal anneal interfaces. Impurity accumulation was measured at HgCdTe/CdTe and CdTe/ZnTe interfaces. Processing anneals were found to nearly eliminate the gettering effect at the in situ Te-stabilized thermal anneal interfaces. Impurities were found to redistribute to the front HgCdTe/CdTe/Si surface and p–n junction interfaces during annealing steps. We also investigated altering the in situ Te-stabilized thermal anneal process to enhance the gettering effect.     

Effect of Cycle Annealing Parameters on Dislocation Density Reduction for HgCdTe on Si

In our previous study of ex situ thermal cycle annealing (TCA) of molecular beam epitaxy (MBE)-grown mercury cadmium telluride (HgCdTe) on CdTe/Si(211) composite substrates we showed consistent dislocation density reduction to ~1 × 10⁶ cm⁻². In this work, we have extended our study to understand the effects of TCA at lower temperatures and fewer cycles than studied previously. By examining TCA performed at the lower end of the temperature spectrum (as low as 385°C), we are able to show an exponential correlation between etch pit density (EPD) and temperature. Varying the number of cycles also shows a similar exponential correlation with EPD. These results suggest that these are the two major factors driving dislocation annihilation and/or coalescence. In this paper, we discuss the theoretical mechanism behind dislocation reduction, both at the surface and throughout the bulk of the HgCdTe layer.     

Dislocation Analysis in (112)B HgCdTe/CdTe/Si

High-quality (112)B HgCdTe/Si epitaxial films with a dislocation density of ??9 × 10⁵ cm^?2 as determined by etch pit density (EPD) measurements have been obtained by thermal cyclic annealing (TCA). The reduction of the dislocation density by TCA has led to a simple rate-equation-based model to explain the relationship between dislocation density and TCA parameters (time, temperature, and number of anneals). In this model, dislocation density reduction is based on dislocation coalescence and annihilation, assumed to be caused by dislocation motion under thermal and misfit stress. An activation energy for dislocation motion in n-type (112)B HgCdTe/Si of 0.93 ± 0.1 eV was determined. This model with no adjustable parameters was used to predict recent TCA annealing results.     

MBE原位碲化镉钝化的碲镉汞长波光电二极管列阵

采用分子束外延(MBE)技术在表面生长碲化镉(CdTe)介质膜的p型碲镉汞(HgCdTe)材料,并通过离子注入区的光刻、暴露HgCdTe表面的窗口腐蚀、注入阻挡层硫化锌(ZnS)的生长、形成p-n结的B+注入、注入阻挡层的去除、绝缘介质膜ZnS的生长、金属化和铟柱列阵的制备等工艺,得到了原位CdTe钝化的n+-on-p...