Nonsaturated integrated injection logic

Conventional integrated-injection-logic structures suffer from strong saturation of the n?p?n transistors. This increases the storage time, and hence puts a limitation on the propagation delay of the structures. A current-control technique is given to reduce this effect without changing the basic i.i.l. structure.     

Folded-collector integrated injection logic

Folded-collector I/SUP 2/L offers an effective method of controlling the saturation of the n-p-n transistor simply by controlling the ratio of two areas: the area of the output collector(s) and the area of a `dummy' collector. This extra collector is folded back and connected to the input base. The structure improves the minimum delay of the basic I/SUP 2/L gate. Moreover, the structure has many circuit applications where a current scaling factor is required, e.g., threshold and ternary logic. Some of these circuits are given.     

New v-groove integrated injection logic

A new V-groove integrated injection logic (v.i.i.l.) is proposed which combines the V-groove technology and the double-diffused bipolar technology. The fabrication processes arc qualitatively described. The lateral p?n?p transistor of the i.i.l. is located on the vertical V-shape surface, and the effective base width is controlled by the combination of the vertical diffusion process and the V-groove etching rate. A 1-dimensional analysis is used and an approximate expression for the collector current of the lateral p?n?p transistor is given. The v.i.i.l. is expected to have a higher production yield than that of the ordinary i.i.l.     

Device physics of integrated injection logic

After a brief review of relevant device parameters, characterizing the inversely operating multicollector n-p-n transistor and the lateral p-n-p transistor which make up anI^{2}Lbasic cell, some electronic circuit properties of this gate are discussed quantitively. Analytic expressions are derived for the transfer characteristics, the noise margin and the propagation delay time per gate in relation to the cell geometry, fan-out, doping profiles, and recombination properties. These expressions are compared with experimental and numerical circuit simulation results.     

The development of heterojunction integrated injection logic

The development of heterojunction integrated injection logic (HI ²L) since 1982 is described. The baseline process that uses AlGaAs/GaAs emitter-down HBTs (heterojunction bipolar transistors) as the switching element is presented. Two sets of design rules, one using a 7.0-μm collector and 8.0-μm metal pitch and another using a 5.0-μm collector and 5.0-μm metal pitch, have been developed for the pilot line circuit fabrication. Typical propagation delays obtained for a fan-out=4 HI²L gate using the 7.0- and 5.0-μm collector processes are 250 and 150 ps, respectively, at a power dissipation of 5 mW per gate. LSI and VLSI circuits as complex as 4 K-gate arrays and 32-bit MIPS microprocessors have been fabricated successfully using the HI²L technology     

Vertical current components in integrated injection logic

Analytic expressions representing a double diffused transistor impurity profile are used to calculate the current components in IIL structures. The expression for the hole current is given for IIL structures with the epitaxial layer grown on a wide n⁺substrate and for buried layer structures. It was found that an equivalent recombination velocity at the n-n⁺interface,S_{nn+}, is of order 10²higher in buried layer structures than in structures with the epitaxial layer grown on a wide n⁺substrate for comparable doping levels. Results obtained using the analytic expressions are compared with those obtained using a computer program which includes heavy doping effects and doping level mobility dependence. Both calculated and computed results are also compared with measured currents for a given IIL structure with the epitaxial layer grown on a wide n⁺substrate. The calculated and the computed results are in good agreement with the experimental results.     

中波红外焦平面列阵探测器γ辐照效应

报道了γ射线辐照对薄膜材料碲镉汞(Hg1-xCdxTe)制备的中波红外焦平面列阵探测器性能的影响.γ射线辐照的剂量依次为3×106 rad、9×106rad、2×107 rad.测量了器件在辐照前及各个剂量辐照后的I-V特性、黑体响应、噪声等性能参数.通过分析实验数据,发现器件的暗电流,噪声随辐照剂量的增加而增大,黑体响应随辐照剂量的增大而减小.其中I-V特性受辐照影响最大,黑体响应和噪声对辐照不是很敏感.这些表明随着辐照剂量的增加,器件的性能逐步衰退.     

Gamma radiation effects on RF MEMS capacitive switches

Dielectric-based RF MEMS capacitive switches were fabricated and characterized for their response to dielectric charging, thermal storage and cycling and to total dose gamma irradiations. The evolution of the switch electromechanical and RF characteristics (actuation and releasing voltages, insertion losses, isolation) were evaluated as a function of the applied stress (temperature or total ionizing dose). It is indicated that the thermal stress has a relatively minor impact on the switches (the switches remained functional with nearly the same electrical properties). Under our particular test conditions, C(V) and S-parameters measurements show that gamma radiation has low to moderate effects on the components behavior.     

Isoplanar integrated injection logic: a high-performance bipolar technology

A newly developed technology is discussed. The emphasis of this approach is on achieving high packing density and high performance by use of various process innovations combined with topological design variations. Factors affecting packing density, DC as well as power delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. The results of computer simulations and measured device parameters and power delay are given. The following gate performance has been obtained at 100-/spl mu/A injector current, /spl beta/u/spl sime/2-4 for all four collectors, speed <10 ns for fan-out of four, speed <5 ns for a fan-out of one. At low currents a speed power product is 0.15 pJ. A packing density of more than 300 gates/mm/SUP 2/ including interconnect and power bussing has been achieved.     

Gate delays of InGaAs/InP heterojunction integrated injection logic

The delay time of an InGaAs/InP heterojunction bipolar transistor integrated injection logic gate is calculated as a function of the npn transistor upward current gain and for fan-outs of one and four. It is shown that intrinsic gate delays under 300 psec are possible with a fan-out of 4 for a gate designed with 3 µm design rules and having 0.5 µm npn and pnp base widths. Gate delays well under 100 psec are predicted for less conservative designs.     

Gamma radiation effects on erbium-doped fiber in superfluorescent fiber source

The radiation effects of two erbium-doped superfluorescent fiber sources (SFSs) are studied in gamma ray environment. Two types of output spectrum profile (twin-peaked spectrum and single-peaked spectrum) of SFSs are constructed by different configuration and parameters. The dependence of radiation-induced power loss and spectra evolution on the dosage is revealed. The results show that the amplitudes of radiation-induced power decrease are quite similar in two SFSs. But the mean wavelength variation of the single-peaked spectrum SFS is approximately 25 times smaller than that of the twin-peaked spectrum SFS. Compared to the twin-peaked spectrum SFS, the single-peaked spectrum SFS presents better radiation tolerance, which should have potential advantages in space applications.     

Specifics of electromagnetic radiation effects on integrated circuits

Modern regulations [1] stress the necessity of testing integrated circuits (ICs) in order to determine the real level of their resistance to single voltage pulses induced by electromagnetic radiation (EMR). With expansion of the EMR spectral composition, however, direct energy release can occur due to the absorption of the EMR field energy by the IC chip itself. To assess this possibility, the relationship is found between different mechanisms of the EMR-induced energy release for the typical irradiation geometry.     

Fabrication and characteristics of ion-implanted GaAs/GaAlAs integrated injection logic inverter

An integrated injection logic inverter has been realised in GaAs/GaAlAs material using ion implantation and Zn diffusion. Si ions have been implanted to merge the current source with the switching transistor, whereas the Be implantation provides the base contact. The shallow p+-emitter of the pnp current source has been fabricated by Zn diffusion. Instead of a lateral pnp transistor, which is typical in I2L technology, a vertical arrangement has been used. This type of transistor shows a better current efficiency and can be fabricated with a better uniformity in terms of base width. First results of an I2L inverter with a vertical pnp transistor are shown.     

High speed integrated injection logic (I/SUP 2/L)

High speed integrated injection logic (I/SUP 2/L) circuits can be manufactured in a process using oxide separation involving a very thin epitaxial layer and ion implantation. Electronic improvements which decrease the charge storage in both the p-n-p and n-p-n transistor are discussed. Analytic expressions are derived which show the consequences for the minority charge stored in the base of the n-p-n transistor and for the influences on the current noise margin. A tradeoff between noise margin and speed is then made. Besides the reduction in delay time, another attractive aspect of this approach is that it allows a simple layout design. By using separate p-n-p and n-p-n transistors, the position of the n-p-n transistors can be adapted to the logic wiring because there is no limitation in the number of crossovers. Some experimental results are given. A minimum value of the propagation delay time of 3 ns has been measured.     

Vertical injection logic

Vertical injection logic (VIL) is a novel form of integrated injection logic (I/SUP 2/L). A vertical p-n-p transistor is used in place of a lateral p-n-p transistor to obtain an improved performance at the same packing density as conventional I/SUP 2/L. The current gain of the p-n-p transistor can be increased, which leads to the excellent power-delay product. The intrinsic delay time is also improved by the action of the bottom injector as a hole sink. The fabrication process and electrical characteristics of VIL are described and contrasted with conventional I/SUP 2/L. A tentative hole sink model is also proposed. The experimental results showed the minimum delay time of 8.8 ns and the power-delay product of 0.07 pJ at low power level below 1 /spl mu/W for VIL compared to 25 ns and 0.18 pJ for standard I/SUP 2/L.     

Oxide-isolated integrated Schottky logic

Integrated Schottky logic has been fabricated in an oxide-isolated technology using 5 /spl mu/m lines and spaces. The novel device uses a merged substrate p-n-p (base width /spl sime/1.0 /spl mu/m) to clamp the collector-base junction of the oxide-walled base, down-operated n-p-n transistor. Ion-implanted low-barrier PtSi-nSi Schottky diodes are used for n-p-n collector decoupling. The average propagation delay measured on a 25-stage ring oscillator (fan-in=fan-out=1) was 2.3 ns at 65 /spl mu/A/stage and 25/spl deg/C. This 150 fJ/V power-delay product is a 3.6/spl times/ improvement compared with 540 fJ/V for junction-isolated ISL (2.7 ns at 200 /spl mu/A/stage).     

Some considerations on high-speed injection logic

After a brief review of the factors that limit the switching speed of standard I/SUP 2/L, the propagation delay time of some special high-speed I/SUP 2/L gates is computed. For a gate realized in oxide-isolated, shallow epitaxial layers, the delay time is directly dependent on the injector base width. Generally, the n-p-n switching transistor hardly contributes to the time delay. For a modified I/SUP 2/L gate in which saturation of the injector is avoided, the delay time is mainly determined by the unity gain frequency of the switching transistor. However, due to the heavy saturation of this transistor, values of /spl tau//SUB d/ already realized indicate that the speed improvement is less than an order of magnitude.     

Characterization of integrated logic circuits

The characterization of integrated logic circuits must be accomplished in a manner which fully accounts for the circuit's nonlinear behavior and is amenable to experimental verification. The approach taken in this paper is to describe both the dc and the transient performance of the circuit by developing nonlinear equivalents of the 2-port "black box" parameters used in specifying linear networks. Such terminal parameter characterization has the obvious advantage of eliminating the need to probe the integrated circuit for testing purposes. In addition, knowledge of terminal performance is a necessity when the circuit is studied from a system point of view. In this paper an emitter-coupled logic circuit is used as an example to illustrate the analysis techniques. After accomplishing the terminal parameter characterization of this circuit, attention is directed towards using these results to establish a design procedure. To this end the relationship that exists between power consumption and the circuit safety margins is explored, and the minimum power-delay time product is derived. The analysis accounts for the parasitics which are present in a monolithic integrated circuit and illustrates the use of the nonlinear transistor model.     

Planar GaAs MOSFET integrated logic

Selective and multiple ion implantations directly into a semi-insulating GaAs substrate were utilized to fabricate planar integrated circuits with deep-depletion plasma-grown native oxide gate GaAs MOSFET's. 1.2-µm gate 27-stage enhancement/depletion (E/D) type ring oscillators, with the circuit optimized to reduce parasitic capacitance, were fabricated (using conventional photolithography) to assess the speed-power performance in digital applications. A minimum propagation delay of 72 ps with a power-delay product of 139 fJ was obtained, making these devices the fastest among current GaAs and Si logic fabricated by conventional photolithography. A minimum power-delay product of 36 fJ with a propagation delay of 157 ps was obtained. The power-delay product is comparable with that of 1.2-µm gate GaAs E-MESFET logic, and the speed is more than twice as great. This paper includes a comparison of the theoretical cut off frequency of MESFET and MOSFET logic devices operating in depletion mode. Results indicate that MOSFET logic has superior potential for high-speed operation.     

Transistor Schottky-barrier-diode integrated logic circuit

A new high-speed low-power logic circuit using Schottky barrier diodes to avoid saturation of bipolar transistors is described. An experiment using discrete devices and a theoretical calculation show the possibility of subnanosecond logic using a saturated-type transistor logic circuit. A theoretical comparison with CML shows a 2:1 advantage in the speed-power product. The compatibility of Schottky barrier diode with monolithic silicon integrated circuit processing is shown. A prototype TTL circuit is described. Experimental results are given.