共查询到20条相似文献,搜索用时 187 毫秒
1.
利用电荷泵技术研究了4nm pMOSFET的热载流子应力下氧化层陷阱电荷的产生行为.首先,对于不同沟道长度下的热载流子退化,通过直接的实验证据,发现空穴陷阱俘获特性与应力时间呈对数关系.然后对不同应力电压、不同沟道长度下氧化层陷阱电荷(包括空穴和电子陷阱俘获)的产生做了进一步的分析.发现对于pMOSFET的热载流子退化,氧化层陷阱电荷产生分两步过程:在较短的应力初期,电子陷阱俘获是主要机制;而随着应力时间增加,空穴陷阱俘获作用逐渐显著,最后主导了氧化层陷阱电荷的产生. 相似文献
2.
热载流子应力下超薄栅p MOS器件氧化层陷阱电荷的表征 总被引:2,自引:0,他引:2
利用电荷泵技术研究了 4nmpMOSFET的热载流子应力下氧化层陷阱电荷的产生行为 .首先 ,对于不同沟道长度下的热载流子退化 ,通过直接的实验证据 ,发现空穴陷阱俘获特性与应力时间呈对数关系 .然后对不同应力电压、不同沟道长度下氧化层陷阱电荷 (包括空穴和电子陷阱俘获 )的产生做了进一步的分析 .发现对于 pMOSFET的热载流子退化 ,氧化层陷阱电荷产生分两步过程 :在较短的应力初期 ,电子陷阱俘获是主要机制 ;而随着应力时间增加 ,空穴陷阱俘获作用逐渐显著 ,最后主导了氧化层陷阱电荷的产生. 相似文献
3.
4.
5.
基于0.18 μm高压n型DEMOS(drain extended MOS)器件,报道了在衬底电流,Isub两种极值条件下作高压器件的热载流子应力实验,结果发现器件电学性能参数(如线性区电流、开态电阻、最大电导和饱和漏电流)随应力时间有着明显退化.通过TCAD分析表明,这主要是由于持续电压负载引起器件内部界面态的变化和电子注入场氧层,进而改变了器件不同区域内部电场分布所致.同时模拟研究还表明,在,Isub第一极大值条件下应力所致的器件退化,主要是由器件漏/沟道耗尽区域的电场强度增加引起的;而在Isub第二极值条件下的应力诱发器件退化,则主要是由漏端欧姆接触附近的电场加强所致. 相似文献
6.
7.
本对亚微米MOSFET在漏雪崩恒流应力(DAS)条件下热载流子注入引起的退变现象做了实验研究,实验结果表明:在一般的恒流应力条件下,栅氧化层中由空穴注入形成的空穴陷阱电荷对器件特起主要影响作用,恒流应力过程中,任何附加的电子注入都可使器件退变特性发生明显变化。实验结果还证实,漏雪崩应力期间形成的空穴陷阱电荷可明显降低器件栅氧化层的介质击穿特性。 相似文献
8.
报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85. 相似文献
9.
报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85. 相似文献
10.
11.
Jie B.B. Li M.F. Lou C.L. Chim W.K. Chan D.S.H. Lo K.F. 《Electron Device Letters, IEEE》1997,18(12):583-585
Interface traps in submicron buried-channel LDD pMOSTs, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOSTs. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. However, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high 相似文献
12.
In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device. 相似文献
13.
超深亚微米部分耗尽SOI NMOSFET关态应力下前栅和背栅晶体管损伤研究 总被引:1,自引:1,他引:0
The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail. 相似文献
14.
F.V. Farmakis G.P. Kontogiannopoulos D.N. Kouvatsos A.T. Voutsas 《Microelectronics Reliability》2007,47(9-11):1434
Degradation phenomena due to hot carrier stress conditions were investigated in double-gate polysilicon thin film transistors fabricated by sequential lateral solidification (SLS). We varied the hot carrier stress conditions at the front gate channel by applying various voltages at the back-gate. Thus, we investigated the device electrical performance under such stress regimes. As a conclusion, we demonstrate that severe degradation phenomena may occur at the back polysilicon interface depending on the back-gate voltage during stress. The nature of these phenomena becomes evident when the back-gate bias is such that the back interface is coupled or decoupled from the front gate electrical characteristics. 相似文献
15.
16.
The origins of the enhanced AC hot-carrier stress damage are examined. The enhancement in hot-carrier stress damage under AC stress conditions observed with respect to damage under DC stress conditions can fully be explained by the presence of three damage mechanisms occurring during both DC and AC operation: interface states created at low and mid-gate voltages, oxide electron traps created under conditions of hole injection into the oxide, and oxide electron traps created under conditions of hot-electron injection. It is shown that the quasi-static contributions of these mechanisms fully account for hot-carrier degradation under AC stress. The AC stress model is applied to devices from several different technologies and to several different AC stress waveforms. Excellent agreement is obtained in each case. The results demonstrate the validity of the model for frequencies up to 1 MHz. The absence of any transient effect indicates that the model could be applicable at much higher frequencies 相似文献
17.
In this paper a method for the study of hot-carrier induced charge centers in MOSFETs based on a small-signal gate-to-drain capacitance measurement is described. Numerical modeling and simulation is used to provide an understanding of the effects of spatially localized trapped carriers and interface states on this capacitance. Experimental gate-to-drain capacitance results are presented and compared with charge pumping measurements. This method is used to investigate hot-carrier degradation of n- and p-channel MOSFETs after drain avalanche hot-carrier stress conditions. It is concluded that under this stress condition the degradation of both n- and p-channel devices is due to the trapping of majority carriers and the generation of acceptor type interface states in the top half of the silicon bandgap. 相似文献
18.
19.
Hot-carrier degradation and bias-temperature instability of FinFET and fully-depleted SOI devices with high-k gate dielectrics and metal gates are investigated. Thinner SOI results in increased hot-carrier degradation, which can be recovered by junction engineering. FinFETs with (1 1 0) Si active surfaces exhibit degradation of sub-threshold swing after hot carrier stress, indicating generation of interface states. The effect of duty cycle on bias-temperature instability modulates the quasi-steady-state trap occupancy over a broad distribution of electron trapping and de-trapping times. Only the deeper traps remain filled for low duty cycle, and shallower traps are emptied during AC stress. 相似文献
20.
The effects of hot-carrier stress (HCS) on the performance of NMOSFETs and a fully integrated low noise amplifier (LNA) made of NMOSFETs in a 0.18 μm CMOS technology are studied. The main effects of HCS on single NMOSFETs are an increase in threshold voltage and a decrease in channel carrier mobility, which lead to a drop in the biasing current of the transistors. In the small-signal model of the transistor, hot-carrier effects appear as a decrease in the transconductance and an increase of the output conductance. No clear change was observed in the parasitic gate–source and gate–drain capacitances in the devices under test due to hot carriers. The main effects of hot carriers in the LNA were a drop of the power gain and an increase of its noise figure. The input and output matching, S11 and S22, slightly increased after hot-carrier stress. The third- order input-referred intercept point (IIP3) of the LNA improved after stress. This is believed to be due to the improvement of the linearity of the current–voltage (I–V) characteristics of the transistors in the LNA at the particular operating point where they were biased. 相似文献