Polylithic Integration of Electrical and Optical Interconnect Technologies for Gigascale Fiber-to-the-Chip Communication

Polylithic integration of electrical and optical interconnect technologies is presented as a solution for merging silicon CMOS and compound semiconductor optoelectronics. In contrast to monolithic and hybrid integration technologies, polylithic integration allows for the elimination of optoelectronic and integrated optic device-related processing from silicon CMOS manufacturing. Printed wiring board-level and compound semiconductor chip-level waveguides terminated with volume grating couplers facilitate bidirectional optical communication, where fiber-to-board and board-to-chip optical coupling occurs through a two-grating (or grating-to-grating) coupling path. A 27% increase in the electrical signal I/O projected by and 33% increase in the number of substrate-level electrical signal interconnect layers implied by the International Technology Roadmap for Semiconductors (ITRS) projections for the 32-nm technology generation are required to facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication. Buried air-gap channels provide for the routing of chip or board-level encapsulated air-clad waveguides for minimum crosstalk and maximum interconnect density. Optical signals routed on-board communicate with on-chip volume grating couplers embedded as part of a wafer-level batch package technology exhibiting compatible electrical and optical input/output interconnects. Measurements of grating-to-grating coupling reveal 31% coupling efficiency between two slab, nonoptimized, nonfocusing volume grating couplers.     

A low-power silicon on sapphire CMOS optoelectronic receiver using low- and high-threshold devices

We report on the architecture and experimental characterization of a small-footprint optoelectronic receiver for parallel arrays of optical interconnects. The receiver is designed and fabricated in the 0.5-/spl mu/m silicon on sapphire CMOS technology. The circuit design exploits the properties of MOS transistors with three different threshold voltages and the insulating substrate to achieve a low-power, high-speed and compact circuit. The design attains a 7-pJ energy per bit transduction cost when operated at 1 Gbit/s data rates.     

Operation of an optoelectronic crossbar switch containing a terabit-per-second free-space optical interconnect

The experimental operation of a terabit-per-second scale optoelectronic connection to a silicon very-large-scale-integrated circuit is described. A demonstrator system, in the form of an optoelectronic crossbar switch, has been constructed as a technology test bed. The assembly and testing of the components making up the system, including a flip-chipped InGaAs-GaAs optical interface chip, are reported. Using optical inputs to the electronic switching chip, single-channel routing of data through the system at the design rate of 250 Mb/s (without internal fan-out) was achieved. With 4000 optical inputs, this corresponds to a potential aggregate data input of a terabit per second into the single 14.6 /spl times/ 15.6 mm CMOS chip. In addition 50-Mb/s data rates were switched utilizing the full internal optical fan-out included in the system to complete the required connectivity. This simultaneous input of data across the chip corresponds to an aggregate data input of 0.2 Tb/s. The experimental system also utilized optical distribution of clock signals across the CMOS chip.     

Preparation of silicon-on-gallium arsenide wafers for monolithicoptoelectronic integration

A process is described which combines silicon-on-insulator (SOI) and wafer bonding techniques to create thin (≈100 nm) single-crystal silicon layers on oxide coated gallium arsenide wafers for use in optoelectronic integration. Using a GaAs substrate for the integration eliminates the thermal expansion coefficient mismatch problems which have blocked monolithic integration of thick, stress sensitive optoelectronic devices on silicon, without compromising the performance of CMOS circuitry which can be fabricated in very thin, compressively strained silicon layers using SOT techniques     

Passive coupling of InGaAsP/InP laser array and singlemode fibres using silicon waferboard

Passive alignment of semiconductor lasers and singlemode fibres has been achieved for the first time using a micro-machined silicon substrate. Mechanical alignment features fabricated on the substrate surface were used to align the active regions of an InGaAsP/InP laser array to four singlemode fibres held in V grooves. Optical coupling efficiencies have been achieved that are comparable to values obtained using the conventional technique of active fibre manipulation. The approach, called silicon waferboard, offers the potential for low-cost optoelectronic device packaging as well as a means for dense hybrid integration of optoelectronic, electronic and optical components required for multifibre, multichip systems.<>     

Power complexity of multiplexer-based optoelectronic crossbar switches

The integration of thousands of optical input/output (I/O) devices and large electronic crossbar switching elements onto a single optoelectronic integrated circuit (IC) can place stringent power demands on the CMOS substrates. Currently, there is no sufficiently general analytic methodology for power analysis and power reduction of large-scale crossbar switching systems. An analysis of the power complexity of single-chip optoelectronic switches is presented, assuming the classic broadcast-and-select crossbar architecture. The analysis yields the distribution of power dissipation and allows for design optimization. Both unpipelined and pipelined designs are analyzed, and a technique to reduce power dissipation significantly is proposed. The design of a 5.12 Tbit single-chip optoelectronic switch using 0.18-/spl mu/m CMOS technology is illustrated. The pipelined switch design occupies < 70 mm/sup 2/ of CMOS area, and consumes <80 W of power, which compares favorably to the power required in electrical crossbar switches of equivalent capacity.     

Photonic MEMS tunable laser sources

This article covers laser configurations, design and experiments of photonic microelectromechanical systems (MEMS) tunable laser sources. Three different types of MEMS tunable lasers such as MEMS coupled-cavity lasers, injection-locked laser systems and dual-wavelength tunable lasers are demonstrated as examples of natural synergy of MEMS with photonics. The expansion and penetration of the MEMS technology to silicon optoelectronic creates on-chip optical systems at an unprecedented scale of integration. While producing better integration with robustness and compactness, MEMS improves the functionalities and specifications of laser chips. Additionally, MEMS tunable lasers are featured with small size, high tuning speed, wide tuning range and CMOS compatible integration, which broaden their applications to many fields.     

Monolithic digital galvanic isolation buffer fabricated in silicon on sapphire CMOS

A monolithic four-channel digital galvanic isolation buffer in the 0.5 /spl mu/m silicon on sapphire (SOS) CMOS technology is reported. Advantage is taken of the insulating properties of the sapphire substrate to integrate on the same die both the isolation structure and the interface electronics. Each isolation channel has been tested to operate at data rates over 100 Mbit/s. The system can tolerate ground bounces of 1 V//spl mu/s and is tested for 800 V isolation. The system includes an integrated isolation charge pump to power the input circuit and is hence capable of operating from a single 3.3 V power supply.     

Low-stress hybridisation of emitters,detectors and driver circuitry on a silicon motherboard for optoelectronic interconnect architecture

In the absence of a truly integrated silicon optoelectronics technology, manufacturable hybridisation technologies for III–V optoelectronic components, compatible with silicon and CMOS substrates, are essential for optoelectronic interconnect. The hybridisation technology for a clock distribution optical interconnect architecture is reported. A substrate removal technology for an 8×8 array of 10 μm thick VCSEL coupons is described, and the performance of AlAs and AlGaAs etch stop layers is discussed. Optoelectronic systems which depend on the retention of the polarisation specific nature of components restrict the mechanical constraints on their manipulation and bonding, to avoid stresses which could destroy the polarisation specificity of the component. A low-stress pick and place technology using a mask aligner has been employed. Eight hundred and fifty nanometres top-surface emitting GaAs/AlGaAs VCSELs, InGaAs/InP p–i–n photodiode arrays, and high-frequency CMOS silicon driver chips have been hybridised on silicon motherboards using this technology. The factors influencing the choice of bonding materials and the sequence of component hybridisation, including the requirements of subsequent planarisation and wiring processes, are discussed. The sources of alignment error are reported. Examples of working emitters, detectors and driver circuitry hybridised using this technology are presented.     

An Optical Interconnect Transceiver at 1550 nm Using Low-Voltage Electroabsorption Modulators Directly Integrated to CMOS

A low-voltage, 90-nm CMOS optical interconnect transceiver operating at 1550-nm optical wavelength is presented. This is the first demonstration of a novel optoelectronic modulator architecture (the quasi-waveguide angled-facet electroabsorption modulator) in a system. It features a simple electronic packaging via flip-chip bonding to silicon. Devices have a broad optical bandwidth, are arrayed two dimensionally, and feature surface normal, spatially separated, and misalignment-tolerant optical ports. The modulators are driven with a novel pulsed-cascode driver capable of supplying an output-voltage swing of 2 V (twice the nominal 1-V CMOS supply) without overstressing thin-oxide core CMOS devices. At the receiver side, a sensitivity of -15.2 dBm is obtained with an integrating/double-sampling front end. The transceiver includes clock generation and recovery circuitry that enables a data serialization factor of five. At a maximum data rate of 1.8 Gb/s, the optical transmitter, receiver, and clocking circuitry consume 12.6, 4.5, and 6.5 mW, respectively, for a total link electrical power dissipation of 23.6 mW. To the best of our knowledge, this is the first demonstration of an interconnect transceiver operating at 1550 nm with a III-V output device directly integrated to the CMOS.     

Synchronous optical detection unmasked

In this article we presented a new silicon optoelectronic receiver in standard CMOS for synchronous detection of light. Two versions were implemented in a 0.7-μm N-well CMOS technology and tested. In the better version, the light-sensitive junctions were the drains of NMOSFETs. This version operated at up to 180 MHz with external 830-nm light pulses of 176 fJ. Our new receiver shows an excellent trade-off between small size, high speed, and good sensitivity, and is therefore an interesting candidate for applications such as digital optical information transfer between VLSI circuits     

Optical I/O Technology for Tera-Scale Computing

This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 × 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era.     

A 2.5-mW SOS CMOS optical receiver for chip-to-chip interconnect

This paper reports on the design of a differential optical receiver in silicon-on-sapphire (SOS) complementary metal-oxide-semiconductor (CMOS). The low-power characteristics (2.5 mW) and small footprint make it a good candidate for two-dimensional optoelectronic interchip interconnects where the transparency of the substrate facilitates system integration and packaging. A differential transimpedance amplifier (TIA) with positive feedback at the front end extends the bandwidth of traditional differential TIAs when the capacitance of the photodetector is smaller than the capacitance of the gates in the differential pair. The full receiver tested in the 0.5-/spl mu/m ultrathin silicon (UTSi) SOS-CMOS Peregrine process consumes 2.5 mW when operated at or near gigabit rates, with bit-error rates of better than 10/sup -12/ taken at 750 Mb/s.     

Novel Heterogeneous Integration Technology of III–V Layers and InGaAs FinFETs to Silicon

Heterogeneous integration of III–V compound semiconductors to Si substrates is regarded as a necessary step for advancing high‐speed electronics and hybrid optoelectronic systems for data processing and communications, and is extensively being pursued by the semiconductor industry. Here, an innovative fab‐compatible, hybrid integration process of III–V materials to Si, namely InGaAs thin films to insulator‐on‐Si, is reported, and the first III–V FinFET devices on Si are demonstrated. Transfer of crystalline InGaAs layers with high quality to SiO2/Si is accomplished by the formation of a robust interfacial nickel‐silicide (NiSi) bonding interface, marking the first report for using silicides in III–V hybrid integration technology. The performance of optimally fabricated InGaAs FinFETs on insulator on Si is systematically investigated for a broad range of channel lengths and Fin perimeters with excellent switching characteristics. This demonstrates a viable approach to large‐scale hybrid integration of active III‐V devices to mainstream Si CMOS technology, enabling low‐power electronic and fully‐integrated optoelectronic applications.     

High performance fully-depleted tri-gate CMOS transistors

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.     

Performance comparison of substrate coupling effect between silicon and SOI substrates in RF-CMOS technology

Substrate coupling may severely degrade the electrical performances of high-speed and RF integrated circuits. An isolation technique study of parasitic effects due to substrate coupling between two blocks of integrated circuits in an RF CMOS 90 nm technology is presented. Isolation performances are compared for both bulk silicon (Si) and silicon-on-insulator (SOI) substrate. For every substrate, a compact electrical model matching well with measurement results is proposed for test structures composed of 50times50 mum cells surrounded with an appropriate guard ring. An isolation improvement of 10 dB is reached by an additional P-type guard ring placed around one cell and an isolation level of 45 dB is achieved at 1 GHz for bulk Si substrate     

体硅衬底上的CMOS Fin FET

介绍了一种制作在普通体硅上的 CMOS Fin FET.除了拥有和原来 SOI上 Fin FET类似的 Fin FET结构 ,器件本身在硅衬底中还存在一个凹槽平面 MOSFET,同时该器件结构与传统的 CMOS工艺完全相容 ,并应用了自对准硅化物工艺 .实验中制作了多种应用该结构的 CMOS单管以及 CMOS反相器、环振电路 ,并包括常规的多晶硅和 W/Ti N金属两种栅电极 .分析了实际栅长为 110 nm的硅基 CMOS Fin FET的驱动电流和亚阈值特性 .反相器能正常工作并且在 Vd=3V下 2 0 1级 CMOS环振的最小延迟为 14 6 ps/门 .研究结果表明在未来 VL SI制作中应用该结构的可行性     

A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique

This paper describes the circuit design and measurement results of a new CMOS frequency doubler proposed for 5-GHz-band wireless applications. The doubler, which can operate at 1.8 V, was fabricated in a standard 0.18-/spl mu/m bulk CMOS technology which has no extra processing steps to enhance RF performance. A current-reuse circuit-design technique is successfully incorporated into the doubler so as to realize both on-chip input/output matching and adequate conversion gain with low input power drive despite the utilization of the standard bulk CMOS technology. The doubler with a single input/output interface features a bypass resistor placed between common ground and a source node of the second stage FET in the current-reuse topology, thereby improving both input power level and conversion gain while saving waste current. Measurement results under the condition of 5.2 GHz and 1.8 V reveal the following good performance: a 2.7-dB maximum conversion gain, a 0.3-dBm high output power, and a 9-mA low current dissipation are achieved with a 2.6-GHz, -3-dBm input power. With a 7-mA low current dissipation and a -7-dBm low input power, the doubler can deliver conversion gain as high as 0 dB. These measurement results are good agreement with the simulated ones.     

Integrated optoelectronic materials and circuits for optical interconnects

Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs Integrated Optoelectronic Circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC’s are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected.     

256-channel bidirectional optical interconnect using VCSELs andphotodiodes on CMOS

Two-dimensional parallel optical interconnects (2-D-POIs) are capable of providing large connectivity between elements in computing and switching systems. Using this technology we have demonstrated a bidirectional optical interconnect between two printed circuit boards containing optoelectronic (OE) very large scale integration (VLSI) circuits. The OE-VLSI circuits were constructed using vertical cavity surface emitting lasers (VCSELs) and photodiodes (PDs) flip-chip bump-bonded to a 0.35-μm complementary metal-oxide-semiconductor (CMOS) chip. The CMOS was comprised of 256 laser driver circuits, 256 receiver circuits, and the corresponding buffering and control circuits required to operate the large transceiver array. This is the first system, to our knowledge, to send bidirectional data optically between OE-VLSI chips that have both VCSELs and photodiodes cointegrated on the same substrate