Feasibility of BCB as an interlevel dielectric in integrated circuits

This paper investigates the feasibility of using an organic polymer based on benzocyclobutene as an interlevel dielectric material in very large scale integrated (VLSI) circuits. The material is a thermoset resin with attractive electrical and mechanical properties for application as an interlevel dielectric in VLSI circuits. It has a low relative dielectric constant of 2.7. The single coating planarization achieved by spin coating the material is superior to currently used materials and makes it a very attractive material for the fabrication of multilevel metal systems. The planarization properties of this material are presented and compared with those of polyimide. The patterning and dry etching of BCB to define 1 μm vias is described. As the material has limited thermal stability at temperatures greater than 350°C, compatible materials for low via resistivity have been investigated using a double level metal structure. The effect of post metal anneals on via resistivity of various via structures is presented. It is found that a low via resistivity of 3 × 10^-9 gW-cm² without any post metal anneal is obtained by using an AlCu/Pd-AlCu metallurgy.     

Hot-carrier aging of the MOS transistor in the presence of spin-onglass as the interlevel dielectric

The effect of introducing a polysilicate or polysiloxane spin-on glass (SOG) as a component of the interlevel dielectric in a multilevel integrated circuit on the hot-carrier aging of the MOS transistor is discussed. It was found that the presence of SOG led to accelerated aging of the MOS transistor: factors of 20 and 5 for silicate and siloxane, respectively. This effect is attributed to water absorbed in the SOG films. a correlation was found for the hot-carrier aging rate and the amount of absorbed water     

Scattering from an infinite conducting cylinder covered with afinite two-layer dielectric coating (modal approach)

The electromagnetic scattering problem of a conducting infinite circular cylinder partially shielded with a finite two-layer dielectric coating has been analyzed. Cylindrical eigenfunctions with unknown modal coefficients are used to expand the interior EM fields in terms of Fourier-Bessel series. Enforcing field boundary conditions at the dielectric-dielectric interface leads to a single set of modal coefficients for field expansions inside the inner and the outer dielectric layers. Replacing the dielectric coating with the induced polarization sources and utilizing pertinent Green's functions, the dielectric-scattered fields are then formulated in terms of the modal coefficients. Imposing field equivalence conditions yields sets of linear algebraic equations for numerical computation of the unknown modal coefficients and subsequently other parameters of interest. Computed backscattered fields based on the modal technique developed are compared to experimental and numerical data obtained for the 2-D problem of a dielectric coated conducting cylinder     

Analytical solution on interfacial reliability of 3-D through-silicon-via (TSV) containing dielectric liner

Interfacial reliability is a challenging issue in through-silicon-via (TSV) technique. To accurately investigate the interfacial reliability of TSV, this paper developed an analytical solution approach, in which the effects of the liner are considered. The validity of the analytical solution is executed by comparison with finite element simulation results. Results show that two approaches have good agreement, with a deviation within 10%, illustrating the validity of the analytical solution developed in this study. Then, using the developed analytical solution, the effects of via diameter, the liner thickness, and the liner materials of TSV on interfacial reliability are investigated with the steady-state energy release rate (ERR). Analytical results show that the steady-state ERR is not only determined by the coefficient of thermal expansion (CTE) mismatch between adjacent materials, but also affected by the products (E × CTE²) of Young’s modulus (E) and CTE² of the liner. Liner materials with lower E × CTE² values will lead to lower steady-state ERR. Additionally, the combined effects of copper via diameter and liner thickness on ERR declare that the ERR highly depends on copper via diameter.     

Oxynitride gate dielectric grown in nitric oxide (NO): the effectof reoxidation on dielectric reliability of the active edge

Reoxidation of an oxynitride gate dielectric grown by NO anneal of thermal oxide has been studied. This process has demonstrated ~3-5X improvement of Q_BD of active edge intensive capacitors in comparison to thermal oxide, N₂O and NO oxynitride. This improvement is believed to be due to the reduction of local thinning of the gate dielectric at the field oxide edge which also reduces local build-up of positive charge near the gate electrode at the isolation edges     

Simulation of system backend dielectric reliability

Backend dielectric breakdown degrades the reliability of circuits. A methodology to estimate chip lifetime due to backend dielectric breakdown is presented. It incorporates failures due to parallel tracks, the width effect, field enhancement due to line ends, and variation in activity and temperature. Different workloads are considered as well, in order to evaluate aging effects in microprocessors running real-world applications with realistic use conditions.     

Challenges of integration of high-κ dielectric with III–V materials (Invited Paper)

This paper gives a brief overview of some of the challenges and approaches of integration of high dielectric constant (high-κ) dielectrics with compound semiconductor materials for future high performance low power logic applications. Reviewed themes include interface passivation layer, atomic layer deposition self-cleaning effects and characterization of dielectric/III–V interfaces.     

IntegraBus increases reliability of new BP Solar module

BP Solar’s newest PV module, the BP 3125 with a 125 W/12 V specification, marks the debut of the company’s IntegraBus technology, in a 157×157 mm multicrystalline cell, which the company claims is the largest cell currently available commercially.Visit www.re-focus.net for the latest renewable energy industry news     

S波段高功率T/R组件的小型化和高可靠设计

介绍了一种S波段高功率T/R组件的小型化和高可靠设计技术。组件整体采用了一种＂三明治＂式电路结构形式,并使用多层微波复合介质基板完成高密度互连,使用集成双管功放单元和层压串馈功率合成器技术制作高功率密度功放电路。结果表明,用该技术方法研制的S波段高功率T/R组件输出功率可达800 W,重量约3 kg,长期工作稳定可靠。     

From defects creation to circuit reliability - A bottom-up approach (invited)

This paper presents a theoretical framework about interface states creation rate from Si-H bonds at the Si/SiO₂ interface. It includes three mains ways of bond breaking. In the first case, the bond can be broken thanks to the bond ground state rising with an electrical field. In the two others cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows us physically modeling the reliability of MOSFET transistors, and particularly NBTI permanent part, and Channel Hot Carrier (CHC) to Cold Carrier (CCC) damage. Finally, the translation of these physical models into reliability spice models is discussed. These models pave the way to Design-in Reliability (DiR) approach which seeks to provide a quantitative assessment of reliability - CMOS device reliability in this case - at design stage thereby enabling judicious margins to be taken beforehand.     

TR组件焊接可靠性工艺研究与应用

对毫米波TR(transmitter and receiver)组件焊接过程中线膨胀系数(CTE)失配机理和由于CTE失配导致的热机械应力对组件可靠性的影响进行了分析。根据阶梯焊接温度精确控制和无铅焊料可靠浸润的要求,从实践中总结出了一种真空预镀涂焊接新工艺。实践表明,该新工艺可以精确地进行阶梯焊接温度控制,使无铅焊料有很好的浸润效果,焊透率由70%以下提高到98.3%,延长了CTE不匹配造成的疲劳失效发生时间,提高了TR组件使用可靠性。     

Assessing the reliability and degradation of photovoltaic module performance parameters

Photovoltaic (PV) modules are renowned for their reliability. However, some modules degrade or even fail when operating outdoors for extended periods. To reduce the degradation, and the number of failures, extensive research is needed on the performance of PV modules. The aim of this study was to establish a photovoltaic degradation and failure assessment procedure. This procedure should assess all parameters of PV modules to completely analyze any observed degradation or failure. In this paper some degradation modes of PV modules are discussed and a procedure used to assess these degradation modes is then presented. Results obtained by subjecting Copper Indium Diselenide (CIS), single and triple junction amorphous silicon (a-Si and a-SiGe), Edge-defined Film-fed Growth (EFG) silicon and mono-crystalline silicon (mono-Si) modules to the assessment procedure are presented and discussed. Results obtained indicate that the thin-film modules degrade by up to 50% in performance after an initial outdoor exposure of 130 kWh/m/sup 2/. Visual inspection revealed that both crystalline modules had cracked cells. The mismatch due to the cracked cell in the EFG-Si module, however, was limited by the interconnect busbars. This paper accentuates the importance of characterizing all module performance parameters in order to analyze observed degradation and failure modes.     

160-Gb/s polarization insensitive all-optical demultiplexing usinga gain-transparent ultrafast nonlinear interferometer (GT-UNI)

We report on a polarization-insensitive all-optical demultiplexer based on gain-transparent operation of a semiconductor optical amplifier in an ultrafast nonlinear interferometer (GT-UNI) using polarization diversity. Error-free demultiplexing from 160 to 10 Gb/s is demonstrated     

On the optimum thickness to test dielectric reliability, in an integrated technology of power devices

This paper deals with the extensive characterization of dielectric films with thicknesses from 20 to 65 nm. Thick dielectric reliability has been investigated with time dependent dielectric breakdown (TDDB). TDDB tests are conducted under constant current injection. Assuming that the logarithm of the median time-to-failure is described by a linear electric field dependence, a generalized empirical law for the long-term reliability of the dielectric is proposed. This law takes into account the applied electric field and the dielectric thickness. This reliability law is available for dielectric thicknesses greater than 10 nm. A procedure to test dielectrics of various thicknesses is given in order to predict their reliability in power integrated devices.     

基于AVR单片机的高可靠性开关量模块的设计

从提高开关量输入输出模块可靠性的角度出发,针对微处理器软件看门狗的漏洞及死机恢复后控制状态保持的特点,给出两套解决方案。模块以功能集成度较高ATmega64L单片机为主控芯片,采用三电源供电,对数据采集和数据通信硬件均采用光电隔离技术,给出软硬件设计的详细过程;模块数据通信采用MODBUS_RTU通信协议,并给出了力控软件调试界面。模块设计体现了抗干扰能力提高的同时,更靠近实用化、工业化、产品化。     

电源模块冗余热备份对可靠性的影响

温度是影响电子设备可靠性的重要因素。介绍了高频开关电源可靠性指标MTBF的计算方法,并分析了电源模块不同热备份数量对可靠性的影响。     

Thermo-mechanical reliability analysis of a RF SiP module based on LTCC substrate

The RF SiP module based on LTCC substrate has attracted considerable attention in wireless communications for the last two decades. However, the thermo-mechanical reliability of this 3D LTCC architecture has not been well-studied as common as its traditional ceramic package structure. A practical RF SiP module based on LTCC substrate was presented and its thermo-mechanical reliability was analyzed in this paper, with emphasis on the reliability of heat reflow process, the operating state and fatigue of second-level solder joints. The configuration and assembly process of the SiP module were briefly introduced at first, and qualitative analysis was made according to the reliability problem that may occur in the manufacturing process and the operating state. Through FEM simulation, this paper studied the warpage and stress variation of the RF SiP module, as well as parametric studies of some key package dimensions. Solder joint reliability under temperature cycling condition was also analyzed in particular in this paper. The results show that for the heat reflow process and operating state, the maximum warpage is both on the top LTCC substrate, but the maximum stresses are on the outermost solder ball and the kovar column at the corner, respectively. There is a large residual stress on the critical solder ball at the end of the reflow process and the key package dimensions has little effect on it. The thickness of top LTCC substrate has a significant impact on the thermal deformation and thermal stress, followed by the height of kovar columns. The reason for the considerable thermal stress on the kovar column is the non-uniform of temperature distribution. The key to reducing thermal deformation and stress in the operating state is the employment of effective cooling measures. It is found by comparison that the reliability of critical solder joints can be greatly improved by adding suitable underfill.     

基于BGA互联的毫米波模块三维集成设计

设计了一种利用微波基板作为转接板的毫米波系统级封装（System in Package,SIP）模块。采用球栅阵列(Ball Grid Array,BGA)作为射频信号层间垂直互联传输和隔离结构,实现了三维集成毫米波模块的低损耗垂直传输。对样件测试结果显示,在28~31 GHz频率范围之间,其端口驻波小于1.5,增益大于30 dB。该三维集成结构简单,射频传输性能良好,其体积仅为传统二维平面封装结构的20%,实现了模块的小型化,可广泛用于微波和毫米波电路与系统。     

On thermo-mechanical reliability of plated-through-hole (PTH)

The mechanical properties of plated copper in plated-through-hole (PTH) were investigated experimentally by a thermo-mechanical analyzer, a nano-indenter, and an acoustic emission instrument. Coefficients of fatigue life prediction models for plated copper have been determined by different failure criteria. Afterwards thermal fatigue test of PTH at three different diameters were performed, and Weibull statistics was employed to evaluate the fatigue life of samples under different failure criteria. Finally, the strain variation of PTH during thermal cycle has been simulated by the finite element analysis (FEA) so as to predict its fatigue life by the selected models. From the comparison of the estimated fatigue life and its experimental results, it is found that the error can be minimized to be within 100%, provided that the drifting of electrical resistance by 20% is used as failure criteria and total strain amplitude is used as control variable in fatigue life prediction model. Based on these findings, design of PTH in printed circuit board (PCB) can be optimized by FEA. It is concluded that fatigue life of PTH will increase with lesser PCB layers, smaller depth-to-diameter ratio, higher PTH density and thicker plated copper.