一种低功耗双重测试数据压缩方案

随着集成电路制造工艺的发展,VLSI（Very Large Scale Integrated）电路测试面临着测试数据量大和测试功耗过高的问题.对此,本文提出一种基于多级压缩的低功耗测试数据压缩方案.该方案先利用输入精简技术对原测试集进行预处理,以减少测试集中的确定位数量,之后再进行第一级压缩,即对测试向量按多扫描划分为子向量并进行相容压缩,压缩后的测试向量可用更短的码字表示;接着再对测试数据进行低功耗填充,先进行捕获功耗填充,使其达到安全阈值以内,然后再对剩余的无关位进行移位功耗填充;最后对填充后的测试数据进行第二级压缩,即改进游程编码压缩.对ISCAS89基准电路的实验结果表明,本文方案能取得比golomb码、FDR码、EFDR码、9C码、BM码等更高的压缩率,同时还能协同优化测试时的捕获功耗和移位功耗.     

双游程编码的无关位填充算法

双游程编码是集成电路测试数据压缩的一种重要方法,可分为无关位填充和游程编码压缩两个步骤.现有文献大都着重在第二步,提出了各种不同的编码压缩算法,但是对于第一步的无关位填充算法都不够重视,损失了一定的潜在压缩率.本文首先分析了无关位填充对于测试数据压缩率的重要性,并提出了一种新颖的双游程编码的无关位填充算法,可以适用于不同的编码方法,从而得到更高的测试数据压缩率.该算法可以与多种双游程编码算法结合使用,对解码器的硬件结构和芯片实现流程没有任何的影响.在ISCAS89的基准电路的实验表明,对于主流的双游程编码算法,结合该无关位填充算法后能提高了6%-9%的测试数据压缩率.     

一种低开销的压缩解压缩方法

针对LED大屏幕显示信息特点,深入分析RLE编码算法.改进游程长度编码模型,并结合Golomb码优势,提出了基于Golomb码的混合游程编码方法;其中分析了任意概率分布下Golomb码的结构,推导出任意给定阶数m和概率分布下的统一编码算法;最后给出了实现解码的硬件电路.通过对不同压缩方式比较,证明本文方法是一种低开销的、简便的、压缩效率高的方法.     

应用混合游程编码的SOC测试数据压缩方法

本文提出了一种有效的基于游程编码的测试数据压缩/解压缩的算法:混合游程编码,它具有压缩率高和相应解码电路硬件开销小的突出特点.另外,由于编码算法的压缩率和测试数据中不确定位的填充策略有很大的关系,所以为了进一步提高测试压缩编码效率,本文还提出一种不确定位的迭代排序填充算法.理论分析和对部分ISCAS 89 benchmark电路的实验结果证明了混合游程编码和迭代排序填充算法的有效性.     

基于变游程编码的测试数据压缩算法

基于IP核的设计思想推动了SOC设计技术的发展,却使SOC的测试数据成几何级数增长.针对这一问题,本文提出了一种有效的测试数据压缩算法——变游程(Variable-Run-Length)编码算法来减少测试数据量、降低测试成本.该算法编码时同时考虑游程0和游程1两种游程,大大减小了测试数据中长度较短游程的数量,提高了编码效率.理论分析和实验数据表明,变游程编码能取得较同类编码算法更高的压缩效率,能够显著减少测试时间、降低测试功耗和测试成本.     

基于数据相关性的测试数据压缩方法

为了减少测试数据量,提出一种利用数据中大量无关位的特殊相关性进行编码压缩的方法,压缩步骤分两步,先选定参考数据,然后利用相关性将与参考数据兼容的数据块编码为"11",数据互补的数据块编码为"10",弥补了FDR码单一编码的不足.解压结构包括一个与参考数据等长的循环移位寄存器和一个有限状态机,结构简单,与Golomb码和FDR码中需要一个与测试向量等长的循环移位寄存器相比,消耗的硬件资源小.针时ISCAS-89标准电路测试向量集的压缩实验结果表明,该方法可以有效地压缩测试数据.且效果比Golomb码和FDR码更好,硬件开销更小.     

An Efficient Test Data Compression Technique Based on Codes

提出了一种新的测试数据压缩/解压缩的算法,称为混合游程编码,它充分考虑了测试数据的压缩率、相应硬件解码电路的开销以及总的测试时间.该算法是基于变长-变长的编码方式,即把不同游程长度的字串映射成不同长度的代码字,可以得到一个很好的压缩率.同时为了进一步提高压缩率,还提出了一种不确定位填充方法和测试向量的排序算法,在编码压缩前对测试数据进行相应的预处理.另外,混合游程编码的研究过程中充分考虑到了硬件解码电路的设计,可以使硬件开销尽可能小,并减少总的测试时间.最后,ISCAS 89 benchmark电路的实验结果证明了所提算法的有效性.     

一种基于编码的低硬件开销的测试数据压缩方法

提出了一种新的测试数据压缩/解压缩的算法,称为混合游程编码,它充分考虑了测试数据的压缩率、相应硬件解码电路的开销以及总的测试时间.该算法是基于变长-变长的编码方式,即把不同游程长度的字串映射成不同长度的代码字,可以得到一个很好的压缩率.同时为了进一步提高压缩率,还提出了一种不确定位填充方法和测试向量的排序算法,在编码压缩前对测试数据进行相应的预处理.另外,混合游程编码的研究过程中充分考虑到了硬件解码电路的设计,可以使硬件开销尽可能小,并减少总的测试时间.最后,ISCAS 89 benchmark电路的实验结果证明了所提算法的有效性.     

一种基于数据预处理的交替与连续长度码的数据压缩方法

文章提出了一种基于数据预处理的交替与连续长度码的数据压缩方法.它利用了相邻测试向量之间不同位较少的特点,同时也利用了这样的特点,即交替与连续长度码编码突破了仅仅对连续的“0”编码的限制.本文首先对测试集进行预处理,然后用交替与连续长度码对处理后的差分向量集进行编码.本方法可以直接用扫描链作为CSR（Circulating Shift Register）,从而节省了硬件开销,并且本文的方法解压结构简单.对ISCA-89电路的实验结果表明,本方法可以有效地压缩测试数据.     

一种基于测试集分组的广义交替码

测试数据编码压缩是一类重要、经典的测试源划分（TRP）方法。本文提出了一种广义交替码,将FDR码、交替码都看作它的特例;又扩展了两步压缩方法,将原测试集划分成多组,每组采用不同的比值进行交替编码,综合了交替码与两步编码各自的优势,弥补了FDR码,交替码对某些电路测试集压缩的缺陷,得到了较好的压缩率。实验结果表明,与同类型的编码压缩方法相比,该方案具有更高的测试数据压缩率和较好的综合测试性能。     

Enhancement of test data compression with multistage encoding

In this paper, we present two multistage compression techniques to reduce the test data volume in scan test applications. We have proposed two encoding schemes namely alternating frequency-directed equal-run-length (AFDER) coding and run-length based Huffman coding (RLHC). These encoding schemes together with the nine-coded compression technique enhance the test data compression ratio. In the first stage, the pre-generated test cubes with unspecified bits are encoded using the nine-coded compression scheme. Later, the proposed encoding schemes exploit the properties of compressed data to enhance the test data compression. This multistage compression is effective especially when the percentage of do not cares in a test set is very high. We also present the simple decoder architecture to decode the original data. The experimental results obtained from ISCAS'89 benchmark circuits confirm the average compression ratio of 74.2% and 77.5% with the proposed 9C-AFDER and 9C-RLHC schemes respectively.     

一种数据包合并跨层优化编码方案

在传统分层系统中,信息数据包首先在数据链路层进行数据包级的检错码编码,然后一个数据包对应一个信息分组在物理层进行符号级的纠错码编码,最后送入信道中传输。为提高系统的传输效率,提出了一种基于数据包合并的物理层与数据链路层编码的跨层优化方案,即数据链路层的多个数据包合并对应物理层的一个信息分组,然后进行纠错编码后再传输。通过理论推导得出了使系统传输效率最大的最优合并数据包个数和数据包长度表达式。通过仿真验证了理论推导的正确性,并与传统方案进行了比较,结果表明,该方案能有效提高系统的传输效率。     

Variable length coding of interleaved DCT coefficients for digital HDTV

This paper proposes an algorithm to redcue the bit-rate for transmission of the quantized DCT coefficient data in digital HDTV coders. The variable length coding compresses the quantized DCT coefficient data by removing their statistical redundancy. Zigzag scan is an effective way to improve the performance of the variable length coding. In order to reduce bit-rate further, we propose a new scanning method. Each DCT block is classified into the interleaving group and the non-interleaving group according to the number of non-zero DCT coefficients, and the DCT blocks in the non-interleaving group are encoded using the segmentation and interleaving of DCT coefficients, and the DCT blocks in the non-interleaving group are encoded using only zigzag scan. Simulation results show that the proposed method improves the bit-rate reduction performance by 6.8% when compared with the conventional method.     

Multiple-symbol parallel decoding for variable length codes

In this paper, a multiple-symbol parallel variable length decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N-bit block of encoded input data stream. The proposed method partially breaks the recursive dependency related to the VLD. First, all possible codewords in the block are detected in parallel and lengths are returned. The procedure results redundant number of codeword lengths from which incorrect values are removed by recursive selection. Next, the index for each symbol corresponding the detected codeword is generated from the length determining the page and the partial codeword defining the offset in symbol table. The symbol lookup can be performed independently from symbol table. Finally, the sum of the valid codeword lengths is provided to an external shifter aligning the encoded input stream for a new decoding cycle. In order to prove feasibility and determine the limiting factors of our proposal, the variable length decoder has been implemented on an field-programmable gate-array (FPGA) technology. When applied to MPEG-2 standard benchmark scenes, on average 4.8 codewords are decoded per cycle resulting in the throughput of 106 million symbols per second.     

An innovative two-stage data compression scheme using adaptive block merging technique

Test data has increased enormously owing to the rising on-chip complexity of integrated circuits. It further increases the test data transportation time and tester memory. The non-correlated test bits increase the issue of the test power. This paper presents a two-stage block merging based test data minimization scheme which reduces the test bits, test time and test power. A test data is partitioned into blocks of fixed sizes which are compressed using two-stage encoding technique. In stage one, successive blocks are merged to retain a representative block. In stage two, the retained pattern block is further encoding based on the existence of ten different subcases between the sub-block formed by splitting the retained pattern block into two halves. Non-compatible blocks are also split into two sub-blocks and tried for encoded using lesser bits. Decompression architecture to retrieve the original test data is presented. Simulation results obtained corresponding to different ISCAS′89 benchmarks circuits reflect its effectiveness in achieving better compression.     

相关瑞利信道下差分空时检测协同分集方案

本文提出了一种采用分布式差分空时分组编码和检测的协同分集方案,在不需要信道状态信息(CSI)的情况下可以实现满分集和全速率发射,并推导了相关瑞利信道下该方案误码率(BER)性能上限的解析表达式。传统的差分空时分组编码对整个码块进行差分,而协同分集下的任何一个协同用户进行差分编码时都不知道整个码块的信息。本文所提出的差分BPSK调制方案,通过将两协同用户的信息分别被调制到相互正交的实轴和虚轴上,从而将码块的联合差分转化为各用户独立差分。分析了在协同用户间不同的信道状态信息(CSI)和协同用户到接收用户不同的CSI情况下本文所提出发射方案的性能。仿真结果表明本文所提出的方案获得了明显的分集增益,同时也较好的吻合了理论分析的结果。     

Improved hybrid layered image compression using deep learning and traditional codecs

Recently deep learning-based methods have been applied in image compression and achieved many promising results. In this paper, we propose an improved hybrid layered image compression framework by combining deep learning and the traditional image codecs. At the encoder, we first use a convolutional neural network (CNN) to obtain a compact representation of the input image, which is losslessly encoded by the FLIF codec as the base layer of the bit stream. A coarse reconstruction of the input is obtained by another CNN from the reconstructed compact representation. The residual between the input and the coarse reconstruction is then obtained and encoded by the H.265/HEVC-based BPG codec as the enhancement layer of the bit stream. Experimental results using the Kodak and Tecnick datasets show that the proposed scheme outperforms the state-of-the-art deep learning-based layered coding scheme and traditional codecs including BPG in both PSNR and MS-SSIM metrics across a wide range of bit rates, when the images are coded in the RGB444 domain.     

MIMO CDMA系统中一种新的循环空时分组编译码方法

该文提出了MIMO CDMA系统中一种新的空时分组编译码方法,称为循环空时分组码(Cyclic Space-Time Block Code,C-STBC),它是将输入信息进行分组循环编码,然后对循环编码后的码字通过不同的天线分别采用不同的扩频码扩频后发射出去。这种CDMA系统下的循环空时分组码对任意的发射天线数都能达到满编码速率和满分集度,且其译码与传统的空时分组码一样简单。仿真结果验证了这种循环空时分组码优于传统的空时分组码。     

一种基于行程长的无损选择加密算法

文中主要介绍了一种基于行程长的无损选择加密方法，首先对图像住平面采用行程长编码，再过滤掉对图像的主体部分不构成影响的短行程，使得所需加密的内容减少，然后对所选的内容进行AES或者基于LFSR的流密码加密，最后对加密方案作了安全性评估，表明这是一个快速安全的选择加密算法．