共查询到18条相似文献,搜索用时 121 毫秒
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根据H.264/AVC的特点,设计出一种适合于帧内预测解码的硬件实现方式,并且引入了帧场自适应模式,有利于提高解码效率,并将该结构配合其他设计好的解码器模块,在FPGA上实现了标准清晰度的H.264视频的实时解码。 相似文献
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H.264指数哥伦布码解码部件的硬件设计和实现 总被引:5,自引:3,他引:2
提出了一种针对H.264视频编码标准的变长码-指数哥伦布码解码的硬件设计结构,对传统的桶形移位器进行优化,主要采用基于PLA的并行解码算法以达到实时解码,同时辅助使用串行解码算法降低硬件资源消耗,保证在能够对符合H.264标准baseline Profile的码流实时解码的基础上优化了电路资源,给出实现该硬件结构对应的FPGA仿真结果及其ASIC硬件规模. 相似文献
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首先简要地叙述了H.264与其他标准相比所具有的优越性,接着系统地阐述了实现H.264全高清解码器的解决方案,并用JM平台对全高清的视频序列进行了解码测试,验证了软解码器方案不具备实时性,采用硬件解码器才是解决全高清视频解码的途径。 相似文献
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设计了一种基于DM642和H.264的网络视觉监控系统。首先,给出了系统的硬件组成结构;然后,介绍了H.264压缩算法;最后,结合H.264压缩算法,给出了系统软件实现方法。该系统可实现异地监控,具有良好的推广应用价值。 相似文献
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H.264是最新的视频编码国际标准,是图像通信研究领域的热点问题之一,利用高性能数字信号处理器来实现H.264实时编解码是一种快速有效的方法,有助于H.264视频标准的迅速推广和应用。TI公司生产的DM64X系列芯片具有很强的并行处理能力和信号处理功能,是实现H.264编解码的理想平台。给出视频编解码在DSP中实现的一些关键问题,针对DM642的整体系统方案,设计出为H.264的实时实现搭建了良好的硬件平台,并给出系统的性能测试结果。解码速度达到了实时的效果,图像主观质量较好,无明显方块效应,码率也比较低。 相似文献
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新一代的压缩标准H.264以其高压缩率与高图像质量而备受青睐,将H.264集成于SoC(片上系统Sys-tern on chip)已成为必然的发展趋势.基于开源免费的32位OpenRISC1200 CPU,设计了H.264解码器SoC系统,系统以OpenRISC1200为核心控制模块,其他所有外围模块包括H.264解码... 相似文献
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研制了一种基于H.264移动视频监控系统,采用i.MX27芯片作为嵌入式CPU芯片,片内集成了H.264硬件编解码视频处理单元。从系统的硬件设计和软件设计两部分介绍了系统的视频采集、压缩、存储、传输及系统控制等方面设计。实验证明,该系统集成度高、成本低、功耗小、功能多而强大,在移动视频监控领域中有广泛的应用前景。 相似文献
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Hamid Reza Nayeri 《International Journal of Electronics》2018,105(8):1261-1272
Video compression performance of High Efficiency Video Coding (HEVC) is about twice of H.264/AVC video compression standard. The improvement in coding efficiency in HEVC is achieved by considerable increase in the computational load compared to H.264/AVC which is substantially very computational intensive. One of the units in HEVC which has changed considerably compared to H.264/AVC is Integer Discrete Cosine Transform (IDCT) unit. IDCT in HEVC standard includes 32 × 32, 16 × 16, 8 × 8 and 4 × 4 transforms. In this paper, a hardware solution for implementing the entire inverse IDCTs in HEVC decoder is proposed. The proposed hardware has a resource-sharing pipelined architecture. As a result, the hardware resources and computation time for implementing inverse IDCTs in HEVC decoder are reduced. Synthesis results by using NanGate OpenPDK 45 nm library indicate that the proposed hardware can achieve 222 MHz clock rate and can achieve real-time decoding of 4096 × 3072 video sequences with 70 fps. 相似文献
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An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction‐level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder. 相似文献
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The microprocessor industry trend towards many-core architectures introduced the necessity of devising appropriately scalable applications. While implementing software based video decoding, the main challenges are the optimized partitioning of decoder operations, efficient tracking of dependencies and resource synchronization for multiple parallel units. The same applies for hardware implementations of video decoders where monolithic approaches anticipate scalability of the design and reusability of already implemented core components.In this paper, we propose an intermediate data stream format (Meta Format Stream) which is suited for architectural decomposition of video decoding by replacing the conventional monolithic decoder architecture design with a pipelined structure. The Meta Format is forward-oriented and self contained and multistandard capable, so that processing of Meta Streams is independent of the originating bit stream. Our approach does not require special coding settings and is applicable to accelerated decoding of any standards-compliant bit stream. A H.264/AVC multiprocessing proposal is presented as a case study for the potential our our concept. The case study combines coarse grained frame-level parallel decoding of the bit stream with fine-grained macroblock level parallelism in the image processing stage.The proposed H.264 decoder achieved speedup factors of up to 7.6 on an 8 core machine with 2-way SMT. We are reporting actual decoding speeds of up to 150 frames per second in 2160p-resolution. 相似文献
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Lin C.-C. Chen J.-W. Chang H.-C. Yang Y.-C. Yang Y.-H. O. Tsai M.-C. Guo J.-I. Wang J.-S. 《Solid-State Circuits, IEEE Journal of》2007,42(1):170-182
In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 times 1088@30 Hz) when operating at 120 MHz with 320 mW power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 mum CMOS technology, the proposed design occupies 2.9times2.9 mm2 silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory 相似文献
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H.264主要档次采用的CABAC熵编码技术在提高视频压缩比率的同时,严重增加了编/解码的计算复杂度,嵌入式系统由于其低成本低功耗的要求,需要专用硬件加速器来进行CABAC编/解码。设计了一个高性能H.264 CABAC硬件加速器,该加速器可配置为编码或解码模式,高效地实现CABAC编/解码操作。通过性能评估实验,在220 MHz时钟频率下,该加速器能够实现平均147 Mbps(1.5 cycle/bit)的编码速度和220 Mbps(1 cycle/bit)的解码速度。与软件实现相比,加速器获得50倍以上的性能提升。 相似文献