Synthesis of initializable asynchronous circuits

We show that existing synthesis techniques may produce asynchronous circuits that are not initializable by gate level analysis tools even when the design is functionally initializable. Due to the absence of any initialization sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for these circuits. In this paper, we show that proper consideration of initializability during the asynchronous circuit synthesis procedure can guarantee initializable implementations. We show that the assignment of don't cares during the synthesis procedure affects the initializability of the final implementation. We present a novel implicit enumeration procedure that selectively assigns don't cares to obtain an initializable implementation. Initialization sequences are obtained as a by-product of our synthesis procedure     

一种新的基于最小项逻辑优化的软件设计与实现

文章提出了一个新的产生本源蕴涵项的算法，并形成了相应的组合逻辑电路逻辑综合优化软件，测试表明，它在运算速度和存储性能上都是高效的。     

Redundancies and don't cares in sequential logic synthesis

The relationships between redundant logic and don't care conditions in combinational circuits are well known. Redundancies in a combinational circuit can be explicitly identified using test generation algorithms or implicitly eliminated by specifying don't cares for each gate in the combinational network and minimizing the gates, subject to the don't care conditions.In this article, we explore the relationships between redundant logic and don't care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense, but may be redundant because they do not alter the terminal behavior of a nonscan sequential machine. These sequential redundancies result in a faulty State Transition Graph (STG) that is equivalent to the STG of the true machine.We present a classification of redundant faults in sequential circuits composed of single or interacting finite state machines. For each of the different classes of redundancies, we define don't care sets which if optimally exploited will result in the implicit elimination of any such redundancies in a given circuit. We present systematic methods for the exploitation of sequential don't cares that correspond to sequences of vectors that never appear in cascaded or interacting sequential circuits. Using these don't care sets in an optimal sequential synthesis procedure of state minimization, state assignment, and combinational logic optimization results in fully testable lumped or interacting finite state machines. We present experimental results which indicate that medium-sized irredundant sequential circuits can be synthesized with no area overhead and within reasonable CPU times by exploiting these don't cares.     

Design and evaluation of a bipolar tri-state logic family

A three-valued bipolar logic family utilizing the two conventional TTL logic states plus the high impedance state is described. The functions realized permit the use of existing synthesis algorithms. The noise immunity for such circuits is defined and calculated. A comparison of circuit complexity between the three-valued family and binary TTL is made for three- and two-valued functions with approximately the same number of possible inputs.     

Design error diagnosis in digital circuits with stuck-at fault model

In this paper we describe in detail a new method for the single gate-level design error diagnosis in combinational circuits. Distinctive features of the method are hierarchical approach (the localizing procedure starts at the macro level and finishes at the gate level), use of stuck-at fault model (it is mapped into design error domain only in the end), and design error diagnostic procedure that uses only test patterns generated by conventional gate-level stuck-at fault test pattern generators (ATPG). No special diagnostic tests are used because they are much more time consuming. Binary decision diagrams (BDD) are exploited for representing and localizing stuck-at faults on the higher signal path level. On the basis of detected faulty signal paths, suspected stuck-at faults at gate inputs are calculated, and then mapped into suspected design error(s). This method is enhanced compared to our previous work. It is applicable to redundant circuits and allows using incomplete tests for error diagnosis. Experimental data on ISCAS benchmark circuits shows the advantage of the proposed method compared to the known algorithms of design error diagnosis.     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

A finite state machine based fault tolerance technique for sequential circuits

With technology advancement at the nanometer scale, systems became more subjected to higher manufacturing defects and higher susceptibility to soft errors. Currently, soft errors induced by ion particles are no longer limited to a specific field such as aerospace applications. This raises the challenge to come up with techniques to tackle soft errors in both combinational and sequential circuits. In this work, we propose a finite state machine (FSM) based fault tolerance technique for sequential circuits. The proposed technique is based on adding redundant equivalent states to protect few states with high probability of occurrence. The added states guarantee that all single faults occurring in the state variables of highly occurring states or in their combinational logic are tolerated. The proposed technique has minimal area overhead as only few states need protection.     

Method for evaluation of transient-fault detection techniques

This work introduces a simulation-based method for evaluating the efficiency of detection techniques in identifying transient faults provoked in combinational logic blocks. Typical fault profiles are simulated in campaigns of injections that reproduce output scenarios of fault-affected combinational circuits. Furthermore, a detection technique is proposed and compared to state-of-the-art strategies by using the method presented herein. Results show the capabilities of all studied techniques, providing a rank in terms of their efficiencies in detecting transient faults induced in combinational logic circuits, and analyzing the situations in which soft errors are produced in memory elements.     

Computer Evaluation of a Method for Combinational-Circuit Synthesis in FPGAs

A method is proposed for the synthesis of combinational circuits in FPGAs subject to programmable-resource utilization. The method is evaluated by computer simulation. The circuit-optimization criterion is the degree of utilization of FPGA logic units and interconnects.     

基于概率转移矩阵的时序电路可靠度估计方法

传统的概率转移矩阵(Probabilistic Transfer Matrix,PTM)方法是一种能够比较精确地估计软差错对门级电路可靠度影响的方法,但现有的方法只适用于组合逻辑电路的可靠度估计.本文提出基于PTM的时序电路可靠度估计方法(reliability estimation of Sequential circuits based on PTM,S-PTM),先把待评估时序电路划分为输出逻辑模块和次态逻辑模块,然后用本文提出的时序电路PIM计算模型得到电路的PIM,最后根据输入信号的概率分布计算出时序电路的可靠度.用ISCAS 89基准电路为对象进行实验和验证,实验表明所提方法是准确和合理的.     

Optimal state assignment technique for partial scan designs

The state assignment of a finite state machine greatly affects the delay, area and testability of sequential circuits. To reduce the length and number of feedback cycles, a new state assignment technique based on m-block partitioning is introduced. Following the completion of the proposed state assignment and logic synthesis stage, partial scan design is performed to choose the minimal number of scan flip-flops. Experimental results show that a drastic improvement in testability can be realised while maintaining a low area and delay overhead     

FsmTest: Functional test generation for sequential circuits

This paper presents a new approach to test pattern generation for sequential circuits modeled as finite state machines. This approach is well suited for controller synthesis, because such devices are usually represented as explicit finite state machines. Based on a functional fault model, only a restricted set of transitions of the finite state machine (FSM) is considered for the purpose of testing. A new state discriminating sequence, referred to as EUIO is proposed. Overlapping is accomplished to reduce the test length. In most cases, test length and CPU time requirements are substantially lower compared with gate-level ATPGs. Techniques are also introduced to preserve a high fault coverage. Evaluation on MCNC benchmarks has shown the effectiveness of the test algorithm both at functional and gate levels, while achieving in most cases 100% coverage of single stuck-at faults.     

Phase assignment for synthesis of low-power domino circuits

High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs but domino logic comes at a heavy cost in terms of total power dissipation. A set of results related to automated phase assignment for the synthesis of low-power domino circuits is presented: (1) it is demonstrated that the choice of phase assignment at the primary outputs of a circuit can significantly impact lower dissipation in the domino block, and (2) a method to determine a phase assignment that minimises power consumption in the final circuit implementation is proposed. Preliminary experimental results on a mixture of public domain benchmarks and real industry circuits show potential power savings as high as 34% over the minimum area realisation of the logic. Furthermore, the low-power synthesised circuits still meet timing constraints     

The synthesis method of logic circuits based on the iMemComp gates

The iMemComp is a family of logic gates based on RRAM devices. It has potential advantage on the design of high-performance logic circuits, since the NAND, AND, NOT and transmission iMemComp gates only consume single cycle, respectively. However, the synthesis method of logic circuits based on the iMemComp gates has not been systematically studied before. This work proposes the synthesis method of the row-oriented logic circuits based on the multi-input single-cycle iMemComp gates. The synthesis results show that the circuits generated from the proposed method outperform most of those RRAM based counterparts generated from the previous methods. Furthermore, the synthesis method of the array-oriented iMemComp logic circuits is proposed. The proposed array-oriented method generates the relatively high-performance logic circuits since both the row-based and the column-based single-cycle iMemComp gates are applied, and the generated circuits are relatively area-efficient because the intra-row and inter-row redundancies are utilized in the circuit mapping.     

基于重写规则法的形式验证技术

<正> 一、引言 验证逻辑设计正确性的传统方法是模拟(Simulation),然而随着数字电路规模和功能扩大,模拟方法已不能保证设计的正确性。与此相对,形式验证(formal verification)方法通过对电路结构的形式进行检查和比较来完成验证。它不需要模拟,因而,避开了模拟信号指数上升的问题。形式验证是一个静态分析,它比动态的逻辑模拟具有更大的潜力。 形式验证的一种方法是将其视为自动定理证明:已知一些公理和已成立的引理,证明某一表达式与另一表达式是等价的。美国Illinois技术研究所的A.S.Wojcik用AURA自动定理证明系统进行了逻辑设计的形式验证,AURA用归结原理作自动定理证明,由于归结法会产生大量子句,因此,证明的效率不是很高。     

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger

In VLSIs, soft errors resulting from radiation-induced transient pulses frequently occur. In recent high-density and low-power VLSIs, the operation of systems is seriously affected by not only soft errors occurring on memory systems and the latches of logic circuits but also those occurring on the combinational parts of logic circuits. The existing tolerant methods for soft errors on the combinational parts do not provide enough high tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and a pass transistor. The paper also presents a construction of soft error masking latches (SEM-latches) capable of masking transient pulses occurring on combinational circuits. Moreover, simulation results show that the proposed method has higher soft error tolerant capability than the existing methods. For supply voltage V _DD ?=?3.3 V, the proposed method is capable of masking transient pulses of magnitude 4.0 V or less.     

Co-RAM: combinational logic synthesis applied to softwarepartitions for mapping to a novel memory device

We introduce the application of current techniques for hardware synthesis of combinational logic blocks to large-scale software partitions for eventual implementation of these partitions in a novel memory device called "Co-RAM." The novelty of our approach is based upon the observation that a wide variety of largescale software functionality can be considered "stateless" by conventional hardware synthesis tools and so may be realized as combinational logic. By limiting the functions placed in memory to combinational functions, we eliminate conventional synchronization overhead associated with coprocessors. A significant aspect of Co-RAM is that it is a system design concept that inherently merges hardware and software design styles at the system level, impacting programming styles, system build approaches, and the programmer's view of the underlying machine. A direct consequence of viewing the functionality as combinational is that the system state is not partitioned with the tasks. By Considering Co-RAM functionality to be stateless with respect to system state, Co-RAM functionality is inlined around the advancement of effectively unpartitioned system state. The rules for procedural combinational logic synthesis are shown to apply to a wide variety of software partitions. Results of our investigation project speedups of 8× to 1000× for a range of algorithms of varying problem size and for projected devices ranging from conventional field programmable gate arrays (FPGAs) to highly specific combinational logic devices     

Process variation aware dual-Vth assignment technique for low power nanoscale CMOS design

This paper presents a novel sensitivity-based, transistor-level, dual threshold voltage (V_th) assignment technique for the design of low power nanoscale CMOS circuits. The proposed technique is based on the Plackett-Burman Design of Experiment method (PB-DOE) in which sensitivity of each transistor to delay variation due to change in its V_th is obtained. The various paths in the circuit are categorized into process sensitive and process-insensitive paths. Transistors in the process sensitive paths are assigned a high V_th to reduce the leakage power without affecting performance. The application of the proposed technique to ISCAS-85 C17 benchmark circuit shows 20% reduction in the leakage power as compared to conventional gate-level dual-V_th assignment technique. Moreover, it is shown that the proposed algorithm can be easily extended to assign dual gate length circuits to achieve a further 20% reduction in the leakage power. The robustness of the proposed technique against process variations is demonstrated with extensive Monte Carlo Simulations. The versatility of the proposed approach to reduce the leakage power for a general CMOS circuit is demonstrated using a Manchester carry chain adder.     

Circuit activity based logic synthesis for low power reliableoperations

A system developed to synthesize both finite state machines and combinational logic for low-power applications, called SYCLOP, is described. SYCLOP tries to minimize the transition density at the internal nodes of a circuit to minimize power dissipation during normal operation. As input signal probabilities and transition densities are considered during the synthesis process, a particular circuit can be synthesized in different ways for different applications that require different types of inputs. For the present state inputs to the combinational circuit of a state machine, simulation was used to determine the signal probabilities and transition densities. The algorithm is not limited by the number of bits used for state assignment. The multilevel optimization process extracts kernels so that there is a balance between area and power optimization. Results have been obtained for a wide range of MCNC benchmark examples     

Efficient reliability evaluation methodologies for combinational circuits

Reliability evaluation methodologies have become important in circuit design. In this paper, we focus on the probabilistic transfer matrix (PTM), which has proven to be a gate-level approach for accurately assess the reliability of a combinational circuit with penalty in simulation runtime and memory usage. In order to improve its efficiency, several methodologies based on traditional PTM are proposed. A general tool is developed to calculate the reliability of a circuit with efficient computation methods based on an optimized PTM (denoted as ECPTM), which achieves runtime and memory usage improvement. Experiments demonstrate how the proposed simulation framework, combined with traditional PTM method, can provide significant reduction in computation runtime and memory usage with different benchmark circuits.