Ultra-low-power 2.4 GHz image-rejection low-noise amplifier

An ultra-low-power image-rejection low-noise amplifier (IR-LNA) for 2.4 GHz ZigBee applications based on 0.18 /spl mu/m CMOS technology is presented. By using the third-order active notch filter the proposed IR-LNA can achieve high image-rejection ratio. Measurements show 12 dB gain, 1.8 dB noise figure, 38 dB image-rejection, -3 dBm input third-order intercept point, -18 and -19 dB input and output return loss while dissipating 0.6 mA from a supply voltage of 1.5 V.     

Miniature high selectivity filters using grounded spiral resonators

A novel miniature high selectivity filter designed using a metamaterial resonator based on four grounded spirals (ForeS) is presented. This enables extreme size reduction together with high out-of-band rejection and low insertion loss. A fabricated third-order filter has overall dimensions of lg/4 by lg/15, a 3 dB bandwidth of 3.7% at 1.63 GHz, insertion loss of 23 dB, attenuation greater than 75 dB in the lower stopband and greater than 40 dB up to 2.6 times the centre frequency.     

Voltage-Controlled Ku-Band and X-Band Tunable Combline Filters Using Barium-Strontium-Titanate

Tunable X-band and Ku-band combline bandpass filters using barium-strontium-titanate capacitors fabricated on alumina substrates with through-substrate CuW vias are reported. Under a 0–100 V bias, the X-band filter changes center frequency from 8.75 GHz to 10.96 GHz with 4–8 dB of loss while the Ku-band filter changes center frequency from 11.7 GHz to 14.3 GHz with 6–10 dB of loss. Advances in processing and integration related to the filter fabrication and design are discussed.      

Monolithic 2-18 GHz low loss, on-chip biased PIN diode switches

Two state-of-the-art monolithic GaAs PIN diode switches have been designed, fabricated and tested. These single-pole double-throw (SPDT) switches exhibit insertion losses of 1.15±0.15 dB over a 2-18 GHz band, which is an unprecedented performance in loss and flatness for monolithic wideband switches incorporating on-chip bias networks. Isolation and return loss are greater than 43 dB and 12 dB, respectively, and the input port power handling is 23 dBm at 1-dB insertion loss compression. These performance characteristics were measured at a nominal bias setting of -8 V, which corresponds to 3.7 mA of series diode bias current and a total dc power consumption of 55 mW. The input power at the third-order interception is 40 dBm. The switches can handle up to 31 dBm (1.25 W) at a higher bias of -18 V and 9.3 mA     

A Monolithic Low-Distortion Low-Loss Silicon-on-Glass Varactor-Tuned Filter With Optimized Biasing

A low-distortion varactor-tuned bandpass filter is demonstrated on a high-Q silicon-on-glass technology. The dc bias network is optimized to achieve high linearity, the center frequency of the filter tunes from 2.4 to 3.5 GHz, and the measured loss of the filter is 2-3 dB at 2 GHz, with a stopband rejection of 25 dB. The measured IIP3 of the filter was +46 dBm     

Low-Loss 4–6-GHz Tunable Filter With 3-Bit High-$Q$ Orthogonal Bias RF-MEMS Capacitance Network

This paper presents a low-loss 4-6-GHz 3-bit tunable filter on a quartz substrate using a high-Q 3-bit orthogonal bias RF microelectromechanical systems capacitance network. Detailed design equations for the capacitively loaded coupled lambda/2 resonators and with capacitive external coupling and source-load impedance loading are discussed. Measurements show an unloaded Q of 85-170, an insertion loss of 1.5-2.8 dB, and a 1-dB bandwidth of 4.35plusmn0.35% at 4-6 GHz. The measured third-order intermodulation intercept point and 1-dB power compression point at 5.91 GHz are > 40 and 27.5 dBm, respectively. The unloaded Q can be improved to 125-210 with the use of a thicker bottom electrode. To our knowledge, this is the highest Q tunable planar filter to date at this frequency range.     

A Low Loss X-Band Quasi-Elliptic Ferroelectric Tunable Filter

A compact high quality factor four-pole X-band tunable quasi-elliptic bandpass filter is presented in this letter. The filter is enabled by high-Q ferroelectric barium strontium titanate capacitors and open-loop resonators. The central frequency of 8.35 GHz and the frequency tuning range of 500 MHz (6%) are achieved with a dc bias voltage of 30 V. The selective filter has a fractional 1 dB bandwidth ranging from 5.5% up to 7.3%. The measured insertion loss and return loss are 5.7-3.5 dB and 10.2-7.9 dB, respectively, with a dc bias range of 0 to 30 V. To the best of our knowledge, this is the best analog tunable performance and selectivity in X-band.     

一种高线性Gm-C复数滤波器的设计

针对低电源电压Gm-C复数滤波器线性度不足的问题,提出了一种使用大信号线性化技术的一阶复数带通滤波器。所提出的复数滤波器使用了不平衡差分对和自适应偏置电路两种线性化技术,通过扩展跨导相对恒定的输入电压范围提高滤波器的线性度。滤波器采用UMC 110 nm CMOS工艺设计,中心频率和带宽分别为2 MHz和1 MHz。Cadence仿真结果显示,在1.2 V电源电压下,滤波器功耗为229μW,镜像抑制比(IIR)为18 dB,线性度(输入三阶交调点IIP3)为9.53 dBm,总谐波失真(THD)为-55.7 dB。该复数滤波器电路结构简单、功耗较低,以期能广泛应用于低电源电压的接收机设计。     

A Ka-Band Electronically Tunable Ferroelectric Filter

This letter presents a three-pole tunable Ka-band coplanar filter that includes six high-Q BST ferroelectric capacitors. It tunes from 29 GHz up to 34 GHz (17%) with low bias voltages ranging from 0 V to 30 V. The filter has fractional bandwidths of 9.5–12.2%. It has a good insertion loss for this category of Ka-band ferroelectric filters, which is between 6.9 dB (0 V) and 2.5 dB (30 V). Two tone measurements showed that the filter has a minimum OIP3 of 15 dBm between 0 V and 30 V. The highest OIP3 value is 26 dBm achieved at a dc bias of 30 V.      

60-GHz-band coplanar MMIC active filters

This paper presents the design and performance of 60-GHz-band coplanar monolithic microwave integrated circuit (MMIC) active filters. To compensate for the loss of the passive filter, a resonator composed of a quarter-wavelength line is terminated by a circuit with a constant negative resistance over a wide frequency band. Cross-coupling is introduced to make the attenuation poles on both sides of the passband. We develop two types of two-stage filter: one with medium bandwidth and the other with narrow bandwidth. The former shows an insertion loss of 3.0 dB with a 3-dB bandwidth of 2.6 GHz and a rejection of larger than 20 dB at a 3-GHz separation from a center frequency of 65.0 GHz. This filter also shows a noise figure of 10.5 dB. The latter filter shows an insertion loss of 2.8 dB with a 10-dB bandwidth of 2.1 GHz at a center frequency of 65.0 GHz. It also shows an output power of 5.0 dBm at a 1-dB compression point. The loss variation due to temperature variation is successfully compensated using a gate bias control circuit. The size of the MMIC filters is 2.5 mm/spl times/1.1 mm.     

Peripheral-coupled-waveguide MQW electroabsorption modulator for near transparency and high spurious free dynamic range RF fiber-optic link

Peripheral coupled waveguide (PCW) design has been deployed in InGaAsP multiple quantum-well (MQW) electroabsorption modulator (EAM) at 1.55-/spl mu/m wavelength. PCW enhances the optical saturation power and reduces the optical insertion loss and the equivalent V/sub /spl pi// simultaneously. A radio-frequency link using a 1.3-mm-long lumped-element PCW EAM has achieved experimentally a link gain of -3 dB, at 500 MHz and at input optical power of 80 mW. The corresponding two-tone multioctave spurious-free dynamic range (SFDR) at the same bias is measured at 118 dB/spl middot/Hz/sup 2/3/. The single-octave SFDR at the third-order null bias is 132 dB/spl middot/Hz/sup 4/5/.     

30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology

In this paper, a passive down mixer is proposed, which is well suited for short-channel field-effect transistor technologies. The authors believe that this is the first drain-pumped transconductance mixer that requires no dc supply power. The monolithic microwave integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator CMOS technology. All impedance matching, bias, and filter elements are implemented on the chip, which has a compact size of 0.5 mm/spl times/0.47 mm. The circuit covers a radio frequency range from 30 to 40 GHz. At a RF frequency of 35 GHz, an intermediate frequency of 2.5 GHz and a local-oscillator (LO) power of 7.5 dBm, a conversion loss of 4.6 dB, a single-sideband (SSB) noise figure (NF) of 7.9 dB, an 1-dB input compression point of -6 dBm, and a third-order intercept point at the input of 2 dBm were measured. At lower LO power of 0 dBm, a conversion loss of 6.3 dBm and an SSB NF of 9.7 dB were measured, making the mixer an excellent candidate for low power-consuming wireless local-area networks. All results include the pad parasitics. To the knowledge of the authors, this is the first CMOS mixer operating at millimeter-wave frequencies. The achieved conversion loss is even lower than for passive MMIC mixers using leading edge III/V technologies, showing the excellent suitability of digital CMOS technology for analog circuits at millimeter-wave frequencies.     

应用于S波段的高线性低噪声放大器

采用E-mode 0.25um GaAs pHEMT工艺,2.0mm × 2.0mm 8-pin双侧引脚扁平封装,设计了一款应用于S波段的噪声系数低于0.5dB的低噪声放大器。通过采用共源共栅结构、有源偏置网络和多重反馈网络等技术改进了电路结构,该放大器具有低噪声,高增益,高线性等特点,是手持终端应用上理想的一款低噪声放大器。测试结果表明在2.3-2.7GHz内,增益大于18dB,输入回波损耗小于-10dB,输出回波损耗小于-16dB,输出三阶交调点大于36dB。     

A Wide Tuning Range Gm –C Continuous-Time Analog Filter

A CMOS operational transconductance amplifier (OTA) for low-power and wide tuning range filter application is proposed in this paper. The OTA can work from the weak inversion region to the strong inversion region to maximize the transconductance tuning range. The transconductance can be tuned by changing its bias current. A fifth-order Elliptic low-pass filter implemented with the OTAs was integrated by TSMC 0.18-mum CMOS process. The filter can operate with the cutoff frequency of 250 Hz to 1 MHz. The wide tuning range filter would be suitable for multi-mode applications, especially under the consideration of saving chip areas. The third-order inter-modulation (IM3) of -40 dB was measured over the tuning range with two tone input signals. The power consumption is 0.8 mW at 1-MHz cutoff frequency and 1.8-V supply voltage with the active area less than 0.3 mm²     

A Miniaturized Bandwidth Reconfigurable Bandpass Chip Filter with Semi-lump ed Topology and GaAs pHEMT Technology

A miniaturized reconfigurable bandpass chip filter with semi-lumped topology and Gallium Arsenide pseudomorphic High electron mobility transistor (GaAs pHEMT) technology is proposed. Semi-lumped topology is employed to instead the traditional lumped inductor with microstrip transmission line, which can reduced the size of the tunable filter significantly. Three-order series and shunt resonated bandpass filter is implemented with shorted stubs and metal-insulator-metal capacitors. Two transmission zeros are introduced with the series resonator and the shunted GaAs FET. By tuning the gate bias circuit of the FET, the capacitance of the series resonator is changed and the bandwidth of the filter is adjusted correspondingly. An equivalent circuit model is developed to interpret the mechanism of the proposed filter circuit. A reconfigurable on chip filter sample operated at 10GHz is fabricated to validate the design. Two fractional bandwidth of 14.3％and 23.5％are tuned with bias voltage of the FET, while insertion loss of 2.4dB and 2.2dB are observed with the filter, respectively. The area of the chip filter is 0.86 × 0.96mm2 and is equivalent to an electrical length of 0.08 × 0.09λg2 at center frequency. Measurement results agree well with the simulation ones.     

CMOS continuous-time current-mode filters for high-frequencyapplications

Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 μm n-well CMOS process achieved a -3 dB cutoff frequency (f ₀) of 42 MHz; f₀ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 μA. Using a single 5 V power supply with a nominal reference current of 100 μA, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm²/pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 μm n-well CMOS process to verify the implementation of finite transmission zeros     

A BiCMOS low-distortion 8-MHz low-pass filter

An 8-MHz seventh-degree elliptic-function low-pass filter is described, demonstrating an approach to low-distortion antialias filtering for high-definition video applications. The filter's performance goals are achieved through the use of circuit design principles that capitalize on the strengths of BiCMOS technology. The integrator circuits composing the filter consist of a new wideband low-distortion transconductor circuit and a unique BiCMOS Miller-stage circuit. Integrator time constants are determined by stable RC products, enabling a simplified filter calibration scheme that is insensitive to temperature-induced variations and requires no phaselock circuits. The prototype filter IC, consisting of seven integrators assembled in an active-ladder configuration, was fabricated in a 10-V, 2-μm 2.5-GHz BiCMOS technology that also features thin-film resistors and polysilicon-plate capacitors. Measured results from the calibrated filter show passband flatness of 0.2 dB, with aberrations of less than ±1 dB over a 100°C temperature range. Stopband attenuation meets its designed goal of 60 dB. Driven by 7-V_pp, differential input signals, the filter exhibits less than -72-dBc third-order intermodulation distortion products at 1 MHz. For 5-V_pp inputs at 4 MHz, third-order intermodulation spurs remain below -65 dBc     

Large-area varactor diode for electrically tunable, high-power UHF bandpass filter

An electronically tunable, high-power, UHF (225-400-MHz) bandpass filter which utilizes large-area, high-capacitance varactor diodes has been designed and tested. The varactor diodes with 100-V breakdown potential, uniform impurity density in the active layer and 400-pF capacitance at -8-V bias are used as the tuning elements of the filter. The diodes are fabricated from epitaxial layers grown on high-conductivity silicon substrates. The epitaxial layers include an n⁺transition layer between the substrate and n-type active layer to minimize the growth defects in the n layer which reduce the breakdown potential to a fraction of the theoretical value. Measurements in a test cavity at 151 MHz indicate a diode Q of 190 at -8-V bias. Input power levels of 1-5 W can be accommodated across the tuning range. Insertion loss varies from 4 to 7 dB and intermodulation products are suppressed 30 dB or more for two input tones of 1 W each. This filter exhibits an order-of-magnitude improvement in power-handling capability over present state-of-the-art filters.     

A 12–18-GHz Three-Pole RF MEMS Tunable Filter

This paper presents a state-of-the-art RF microelectromechanical systems (MEMS) wide-band tunable filter designed for the 12–18-GHz frequency range. The coplanar-waveguide filter, fabricated on a glass substrate using loaded resonators with RF MEMS capacitive switches, results in a tuning range of 40% with very fine resolution, and return loss better than 10 dB for the whole tuning range. The relative bandwidth of the filter is$hbox5.7pm hbox0.4hbox%$over the tuning range and the size of the filter is 8 mm$, times ,4$mm. The insertion loss is 5.5 and 8.2 dB at 17.8 and 12.2 GHz, respectively, for a 2-$hboxkOmega/hboxsq$bias line. The loss improves to 4.5 and 6.8 dB at 17.8 and 12.2 GHz, respectively, if the bias line resistance is increased to 20$hboxkOmega/hboxsq$. The measured$ IIP_3$level is$≫$37 dBm for$Delta f ≫ 200$kHz. To our knowledge, this is the widest band planar tunable filter to date.     

Noise and power reduction in filters through the use of adjustablebiasing

A technique that enables the variation of bias currents in a filter without causing disturbances at the output is presented. Thus, the bias current can be kept at the minimum value necessary for the total input signal being processed, reducing the noise and power consumption. To demonstrate this approach, a dynamically biased log-domain filter has been designed in a 0.25-μm BiCMOS technology. The chip occupies 0.52 mm². In its quiescent condition, the filter consumes 575 μW and has an output noise of 4.4 nA rms. Signal-to-noise ratio greater than 50 dB over 3 decades of input and total harmonic distortion less than 1% for inputs less than 2.5 mA peak are achieved. The bias can be varied to minimize noise and power consumption without disturbing the output