Design of a Monolithic CMOS LC-Voltage Controlled Oscillator with Low Phase Noise for 4GHz Frequency Synthesizers

基于0.18μm RF CMOS工艺,采用双端调谐结构实现了一种可应用于WLAN的二次变频收发机的压控振荡器.其输出频率范围可以覆盖收发机所需4.1～4.3GHz的频段,其最大调谐范围为500MHz.在距中心频率4.189GHz为4MHz处的相位噪声为-117dBc/Hz,500kHz处为-107dBc/Hz.输出信号抖动的均方根值为4.423ps,输出功率为-8.68dBm.     

低增益变化宽线性范围低噪声压控振荡器设计

应用TSMC 0.18μm CMOS工艺设计了一款低调谐增益变化,恒定调谐曲线间隔,恒定输出摆幅的低功耗低噪声宽带压控振荡器(Voltage Controlled Oscillator,VCO).本振荡器的振荡频率覆盖1.153~1.911GHz(49.5%)范围,相邻调谐曲线的覆盖范围大于50%,调谐增益变化范围为45.5~52.7MHz/V(13.7%),相邻调谐曲线间距变化范围为43.2~45.9MHz(5.9%),VCO输出波形的峰峰值为694~715mV(3%),调谐曲线的线性范围为0.2~1.6V(1.4V).在1.8V的电源电压下,VCO在中心频率1.53GHz处耗电电流为3.2mA,相位噪声在1MHz频偏处为-130.5dBc/Hz,FOM值为-186.5dBc/Hz.     

一种低调谐增益变化、自适应功率控制的宽带电感电容压控振荡器

本文提出了一种电感电容宽带压控振荡器结构。为解决宽输出频率范围对振荡器调谐增益和起振条件的影响,设计了具有优化单位值的二进制开关可变电容阵列和二进制开关负阻抗阵列。该振荡器采用0.18um工艺制造,其输出频率范围约为1.9-3.1GHz。在1.8V电压下,消耗电流为14.2mA-4mA。测试结果表明,采用本文所提出调谐增益抑制技术,在整个频率调谐范围内调谐增益的变化为50-60MHz/V. 在3GHz频率处1MHz频偏下的相位噪声为-117dBc/Hz.     

一种应用于多频接收机的宽带频率综合器

采用0.18µm 1P6M CMOS工艺实现了一种应用于多频接收机的整数分频频率综合器。该频率综合器为接收机提供频率分别为2.57GHz, 2.52GHz, 2.4GHz 和 2.25GHz的本振信号。为了覆盖要求的频点,其宽带压控振荡器同时采用了可变电容阵列和可变电感阵列。经测试,压控振荡器的频率调谐范围为1.76GHz~2.59GHz。对于频率为2.57GHz, 2.52GHz, 2.4GHz 和 2.25GHz的载波,在1MHz频偏处,相位噪声分别为-122.13dBc/Hz、-122.19dBc/Hz、-121.8dBc/Hz和-121.05dBc/Hz。其带内相位噪声分别为-80.09dBc/Hz、-80.29dBc/Hz、-83.05dBc/Hz 和-86.38dBc/Hz。包括驱动电路在内的芯片功耗约为70mW。芯片面积为1.5mm×1mm。     

低相位噪声压控振荡器的设计及仿真

随着通信技术对射频收发机性能要求的提高,高性能压控振荡器已成为模拟集成电路设计、生产和实现的关键环节.针对压控振荡器设计过程中存在相位噪声这一核心问题,采用STMC 0.18μm CMOS工艺,提出了一种1.115GHz的电感电容压控振荡器电路,利用Cadence中的SpectreRF对电路进行仿真.仿真结果表明:在4~6V的电压调节范围内,压控振荡器的输出频率范围为1.114 69~1.115 38GHz,振荡频率为1.115GHz时,在偏离中心频率10kHz处、100kHz处以及1MHz处的相位噪声分别为-90.9dBc/Hz,-118.6dBc/Hz,-141.3dBc/Hz,以较窄的频率调节范围换取较好的相位噪声抑制,从而提高了压控振荡器的噪声性能.     

2.5 GHz低相位噪声LC压控振荡器

在0.35 μm SiGe BiCMOS工艺条件下,设计了一个全集成的低相位噪声LC压控振荡器(VCO).该VCO采用尾电阻结构替代传统的尾电流源结构实现电流控制,以减小尾电流源产生的噪声.该VCO的调谐范围为480 MHz,可以覆盖2.32～2.8 GHz.当振荡频率为2.5 GHz时,100 kHz和1 MHz频偏处的相位噪声分别为-104.3 dBc/Hz和-124.3 dBc/Hz.振荡器工作电压为5 V,尾电流为5 mA.工作在2.5 GHz时,其100 kHz频偏处的性能系数为-178 dBc/Hz.     

基于0.18μm SiGe BiCMOS工艺的60GHz VCO分析与设计

采用0.18 μm SiGe BiCMOS工艺,设计了一个60GHz的交叉耦合差分压控振荡器(VCO).通过分析传输线的性能,用λ/ 4短路传输线构造谐振回路.在分析VCO相位噪声的基础上,采用噪声滤波技术提高VCO的相位噪声性能.该VCO的工作电压为2.2V,偏置电流为11mA,频率调谐范围为58.377GHz～60.365GHz.当振荡频率为60.365GHz时,1MHz和10MHz频偏处的相位噪声分别为-79.1dBc/ Hz和-99.77dBc/ Hz.     

900 MHz压控振荡器设计

采用集总元件变容二极管和超高频三极管设计900 MHz压控振荡器,根据ADS2006A软件仿真确定了压控振荡器的电路参数,并对相关指标如相位噪声、调谐带宽、稳定系数、输出功率和谐波电平等进行了仿真,通过调整电路参数,优化电路结构,实现了工作频率为1 GHz、调谐带宽为90 MHz的压控振荡器,其相位噪声在偏移中心频率10 kHz处为-105 dBc/Hz,在100 kHz处为-120 dBc/Hz,该设计大大降低了系统成本.     

一种宽带低相噪CMOS LC压控振荡器设计

设计了一种频率可调范围约830MHz全集成CMOS LC压控振荡器.该压控振荡器利用了一种改进的四位二进制加权的开关电容阵列扩大了其调谐范围;采用了可变尾电流源设计,使得振荡信号在整个频率范围内幅度变化不大.结果表明,该压控振荡器总调节范围1.12～1.95GHz,功耗为6.5～19.1mW,采用0.35μm CMOS RF工艺设计版图面积为360μm×830μm,工作于1.1GHz和1.9GHz时,1MHz频偏处的单边带相位噪声分别为-122dBc/ Hz、-120dBc/ Hz.     

低功耗低噪声正交压控振荡器设计

设计了一种用于WLAN 802.11 n收发机频率合成器的新颖低功耗、低相位噪声正交输出LC电压控制振荡器(QVCO)。电路设计中使用了Cadence IC5.033和ADS2004软件以及TSMC0.18μm CMOS工艺模型库,电路依靠并联的耦合支路相互作用使两个独立压控振荡器输出相位成正交,采用PMOS并联耦合支路和开关控制偏置两种新技术降低了VCO的相位噪声,其仿真结果为1 MHz频偏处-128.6 dBc/Hz和10 kHz频偏处-84 dBc/Hz。采用数字电容阵列提高了QVCO的频率调谐范围,QVCO的频率范围仿真结果为3.1 GHz~4.1 GHz。QVCO的电源电压为1.8 V,功耗17 mW。实现了低功耗正交输出压控振荡器,同时通过新颖的电路设计技术改善了相位噪声,改变了正交输出LC压控振荡器高噪声的传统观念,为今后在正交输出LC压控振荡器的设计提供了一些参考。     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.     

SiGe Bipolar VCO With Ultra-Wide Tuning Range at 80 GHz Center Frequency

A SiGe millimeter-wave VCO with a center frequency around 80 GHz and an extremely wide (continuous) tuning range of 24.5 GHz ( ap 30%) is presented. The phase noise at 1 MHz offset is -97 dBc/Hz at the center frequency (and less than -94 dBc/Hz in a frequency range of 21 GHz). The maximum total output power is about 12 dBm. A cascode buffer improves decoupling from the output load at reasonable VCO power consumption (240 mW at 5 V supply voltage). A low-power frequency divider (operating up to 100 GHz) provides, in addition, a divided-by-four signal. As a further intention of this paper, the basic reasons for the limitation of the tuning range in millimeter-wave VCOs are shown and the improvement by using two (instead of one) varactor pairs is demonstrated.     

A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver

This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver.Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output.Measured spurious tones are lower than -60 dBc. The settling time is within 80 μs. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.     

粗调和细调相结合的标准CMOS低噪声环形压控振荡器

本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz～1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。     

A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digitalwireless communication

A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC consisting of receive, transmit, and local oscillator (LO) sections is presented. The transmit section achieves an unwanted sideband suppression of -43 dBc, LO leakage of -59 dBc, and third-order spurious rejection of -70 dBc. The transmit output noise level is -165 dBc/Hz at a 20-MHz offset from the carrier. The on-chip very high-frequency oscillator has a phase-noise level of -106 dBc/Hz at 100-kHz offset when operating at 800 MHz. The receive section has 36 dB of gain with 36 dB of gain range in 12-dB steps. The transceiver IC has been fabricated using a 25-GHz f_t silicon bipolar process and is designed to operate over a supply-voltage range of 2.7-5.0 V     

A 0.6 V, 4.32 mW, 68 GHz Low Phase-Noise VCO With Intrinsic-Tuned Technique in 0.13 $mu$m CMOS

An intrinsic-tuned, 68 GHz voltage controlled oscillator (VCO) without an extra on-chip accumulation-mode metal oxide semiconductor (MOS)-varactor is demonstrated in a standard, 0.13 mum CMOS technology. This VCO exhibits phase noises of -98.4 dBc/Hz and -115.2 dBc/Hz at 1 and 10 MHz offset, respectively, along with a tuning range of 4.5 % even under a small power consumption of 4.32 mW. Besides, the highest figure-of-merit (taking frequency tuning range into account) of -182 dBc/Hz under the 1 MHz offset condition is achieved among all previously reported >60 GHz CMOS-based VCOs, which is attributed to the proposed intrinsic tuning mechanism.     

A 900-MHz 1.5-V CMOS voltage-controlled oscillator using switched resonators with a wide tuning range

A 900-MHz fully integrated VCO was fabricated in a 0.18-/spl mu/m foundry CMOS process. Under 1.5 V power supply, this VCO can be tuned from 667 MHz to 1156 MHz which corresponds to a 53.6% tuning range. The VCO has nearly constant phase noise over the whole tuning frequency, credit to the switched resonators used in this VCO. The phase noise at a 600 kHz offset is -123.1 dBc/Hz at 1125 MHz center frequency and -124.2 dBc/Hz at 667 MHz center frequency.     

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

We present an integrated fractional-N low-noise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is ?87 dBc/Hz and ?106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to ?98 dBc/Hz at 10 kHz and ?111 dBc/Hz at 1 MHz offset, respectively, were measured.     

A 6 GHz high power and low phase noise VCO using an InGaP/GaAs HBT

A 6 GHz voltage controlled oscillator (VCO) optimized for power and noise performance was designed and characterized. This VCO was designed with the negative-resistance (Neg-R) method, utilizing an InGaP/GaAs hetero-junction bipolar transistor in the negative-resistance block. A proper output matching network and a high Q stripe line resonator were used to enhance output power and depress phase noise. Measured central frequency of the VCO was 6.008 GHz. The tuning range was more than 200 MHz. At the central frequency, an output power of 9.8 dBm and phase noise of -122.33 dBc/Hz at 1 MHz offset were achieved, the calculated RF to DC efficiency was about 14%, and the figure of merit was -179.2 dBc/Hz.     

一种简易微波VCO的设计*

描述了一种高性能简易微波VCO器件的设计和实验。该器件基于负阻原理设计,利用微波FET和变容二极管等分立元件制作,具有高性价比的特点。设计过程中利用ADS软件进行电路的匹配和优化,通过合适的外电路设计对变容二极管VCO的调频线性度进行改善,同时,降低了VCO的相位噪声。实际电路的测试结果表明,当该VCO的中心频率为4.3GHz时,其调谐范围大于200MHz,输出功率大于5.2dBm,相位噪声优于-112dBc/Hz@1MHz和-83dBc/Hz@100kHz。