一种用于电视调谐器的宽带CMOS低噪声放大器设计

介绍了一种宽带CMOS低噪声放大器设计方法,采用噪声抵消技术消除输入MOS管的噪声贡献.芯片采用TSMC 0.25μm 1P5M RF CMOS工艺实现.测试结果表明:在50～860MHz工作频率内,电压增益约为13.4dB;噪声系数在2.4～3.5dB之间;增益1dB压缩点为-6.7dBm;输入参考三阶交调点为3.3dBm.在2.5V直流电压下测得的功耗约为30mW.     

CMOS宽带线性可变增益低噪声放大器设计

文章设计了一种48MHz~860MHz宽带线性可变增益低噪声放大器,该放大器采用信号相加式结构电路、控制信号转换电路和电压并联负反馈技术实现。详细分析了线性增益控制、输入宽带匹配和噪声优化方法。采用TSMC0.18μm RF CMOS工艺对电路进行设计,仿真结果表明,对数增益线性变化范围为-5dB~18dB,最小噪声系数为2.9dB,S11和S22小于-10dB,输入1dB压缩点大于-14.5dBm,在1.8V电源电压下,功耗为45mW。     

低噪声宽带放大器的设计实例

低噪声微波放大器是决定雷达接收机灵敏度的关键因素，而宽频带特性又是电子侦察和电磁兼容测量的关键特性。针对上述要求，研制了工作在3-6GHz的C波段低噪声宽带放大器。该场放经某基地使用，证明性能良好，满足军方要求。     

5.6GHz CMOS低噪声放大器设计

分析了一种射频COMS共源-共栅低噪声放大器的设计电路,采用TSMC 90nm低功耗工艺实现。仿真结果表明:在5.6GHz工作频率,电压增益约为18.5dB;噪声系数为1.78dB;增益1dB压缩点为-21.72dBm;输入参考三阶交调点为-11.75dBm。在1.2V直流电压下测得的功耗约为25mW。     

宽带CMOS低噪声放大器的设计

文章主要介绍应用于集群接收机系统的350MHz～470MHz低噪声放大器,采用0.6μm CMOS工艺。探讨了优化低噪声放大器的噪声系数、增益与线性度的设计方法,同时对宽带输入输出匹配进行了分析。这种宽带低噪声放大器的工作带宽350MHz～470MHz,噪声系数小于3dB,增益为24dB,增益平坦度为±1dB,输入1dB压缩点大于-15dBm。     

电视调谐器中电阻负反馈结构的宽带低噪声放大器设计

设计了一种应用于DVB-S标准的数字电视调谐器的宽带放大器.采用电阻负反馈输入匹配结构,把交流反馈和直流偏置结合在一起,在噪声、增益和线性度方面达到了很好的性能,满足射频电视调谐器的应用需要.此低噪声放大器有约2.5 GHz的3 dB带宽,大于20 dB的电压增益,输入匹配优于-14 dB,噪声系数低于3.3 dB,IIP3在2.5 dBm之上.此LNA的输入匹配、线性度、噪声性能作了较为详细的讨论.     

一种用于电视协调器的CMOS无电感互补噪声抵消低噪声放大器设计

本文介绍了一个用于电视协调器的CMOS无电感互补噪声抵消低噪声放大器。放大器包括一个共栅极和一个共源级,实现单端转差分的功能。采用的互补结构能够节省功耗和改善噪声系数。线性度也通过采用多个晶体管并联技术来增强。芯片采用SMIC 0.18μm CMOS 工艺。测试结果表明,在50MHz到860MHz频段内,电压增益达到13.5到16dB,噪声系数小于4.5dB,最小达到2.9dB,在860MHz频率处,输入1dB压缩点为-7.5dBm。核心电路在1.8V电源电压下,消耗6mA电流,芯片面积是0.2×0.2mm2     

一种用于地面和有线接收机的宽带低噪声放大器

提出并设计了一种用于数字电视接收调谐芯片的宽带低噪声放大器.该设计采用0.35μm SiGe BiCMOS工艺,器件的主要性能为:增益等于18.8dB,增益平坦度小于1.4dB,噪声系数小于5dB,1dB压缩点为-2dBm,输入三阶交调为8dBm.在5V供电的情况下,直流功耗为120mW.     

基于ADS仿真的宽带低噪声放大器设计

设计了一个S频段宽带低噪声放大器.该放大器采用两级E-PHEMT晶体管(ATF541M4)级联结构,单电源供电模式.应用微波仿真软件ADS对匹配电路进行了优化设计,最后通过S参数及谐波平衡仿真得到放大器的各项性能参数,在2.7～3.1 GHz频率范围内噪声系数小于0.6 dB,带内增益大于30 dB,带内平坦度小于±1 dB,输入输出驻波比小于1.6 dB,1 dB增益压缩点输入功率不小于-15 dBm.仿真结果表明,该设计完全满足性能指标要求.     

一种专用宽带低噪声前置放大器

描述了一种专用双极单片宽带噪声前置放大器。该放大器的开环增益60dB－3dB带宽2．5MHz,等效输入噪声电压1．6V√Hz。     

A Highly Linear Wideband CMOS Low-Noise Amplifier Based on Current Amplification for Digital TV Tuner Applications

A differential wideband low-noise amplifier (LNA) based on the current amplification scheme is presented for digital TV tuners. In order to highly improve the linearity and exploit the noise cancellation, a common-gate stage with positive current feedback is integrated in parallel with a common-source stage using the current mirror amplifier. The proposed 0.18-mum CMOS LNA exhibits a power gain of 20.5 dB, an IIP3 of 2.7 dBm, an IIP2 of 43 dBm, and an average noise figure of 3.3 dB with 32.4 mW power consumption at a 1.8-V power supply and 0.12 mm² area.     

A CMOS Resistive Feedback Differential Low-Noise Amplifier With Enhanced Loop Gain for Digital TV Tuner Applications

A resistive feedback differential low-noise amplifier (LNA) with enhanced loop gain is implemented as a part of a digital TV (DTV) tuner using a 0.18-$mu{hbox{m}}$ CMOS process. A voltage buffer having higher gain, higher linearity, and lower noise figure (NF) than those of the conventional differential source follower (DSF), which is called the differential hybrid voltage buffer (DHVB) in this paper, is designed by combining the common source amplifier and source follower. By adopting the DHVB with optimized performance as a voltage buffer of the conventional resistive feedback differential LNA, the loop gain of the LNA can be increased. This leads to a highly linear resistive feedback LNA with higher gain and lower NF compared to the conventional resistive feedback LNA. For the wide gain range, the proposed LNA includes the variable gain function based on the resistive attenuator employing the T-switch. The measurement results of the proposed LNA exhibit a maximum gain of 16 dB and a gain range of 50 dB. At maximum gain, the LNA shows an average NF of 2.8 dB, a third-order input-referred intercept point of $-{hbox{1 dBm}}$, a second-order input-referred intercept point of 40 dBm, and S11 of under $-{hbox{9 dB}}$ in a frequency range from 48 to 860 MHz. The power consumption is 30.6 mW at a 1.8-V power supply and the chip area is ${hbox{0.25 mm}}^{2}$.      

A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications

To employ the distributed amplification technique for the design of ultra-wide-band low-noise amplifiers, the poor noise performance of the conventional distributed amplifiers (DAs) needs to be improved. In this work, the terminating resistor of the gate transmission line, a main contributor to the overall DA's noise figure, is replaced with a resistive-inductive network. The proposed terminating network creates an intentional mismatch to reduce the noise contribution of the terminating network. The degraded input matching at low frequencies can be tolerated for ultra-wide-band applications as they need to operate above 3 GHz. Implemented in a 0.13 mum CMOS process, the proposed DA achieves a flat gain of 12 dB with an average noise figure of 3.3 dB over the 3- to 9.4-GHz band, the best reported noise performance for a CMOS DA in the literature. The amplifier dissipates 30 mW from two 0.6-V and 1-V dc power supplies.     

一种低噪声高增益宽带视频对数放大器

着重介绍了一种用于电子对抗系统预警雷达接收机中的低噪声高增益宽带视频对数放大器的设计原理，制造工艺及其应用，进一步考察了国内外整机系统的发展现状，综合介绍了目前国内外视频对数放大器的发展及其在整机系统中的应用前景。     

混合集成低噪声宽带AGC放大器

采用厚膜混合集成工艺，研制出ＳＨ３０９－１低噪声宽带ＡＧＣ放大器，其噪声系数≤１．５ｄＢ，最大输入电平≥４００ｍＶ／５００Ω，增益≥５０ｄＢ，增益控制范围≥５０ｄＢ，工作频率范围为６０ＭＨｚ±１０ＭＨｚ。主要介绍了其设计原理及应用。     

基于BiFET结构的宽带低噪声放大器设计

采用0.35 μm siGe BiCMOS工艺实现了双极型晶体管和场效应管结合结构(BiFET结构)的宽带低噪声放大器.电路的输入端采用切比雪夫带通滤波器实现了宽频带范围的阻抗匹配.版图设计的仿真结果表明,在2～3 GHz的频带范围内,该低噪声放大器的噪声系数为2.2～2.7 dB,增益为20～22.7 dB,输入端反射系数为-17～-12 dB.     

A Multiband Inductor-Reuse CMOS Low-Noise Amplifier

This paper presents the design and implementation of a new multiband, multistandard CMOS low-noise amplifier (LNA) that reuses inductors for different frequency bands to minimize chip area. The idea is to adaptively reconfigure a CMOS transistor in either common source or common gate configuration to achieve narrow-band (NB) or wide-band (WB) input matching, respectively, while conveniently reusing input and load inductors for both bands. This architecture is suitable for 802.11 a/b/g and Public Safety Broadband (PSB) applications, where the NB configuration covers wireless local area network (WLAN) 802.11 b/g, while the WB configuration accommodates the PSB at 4.9 GHz and WLAN 802.11 a. Two versions of the proposed idea, a tapped-capacitor and a tapped-inductor input-matched LNA, have each been designed and fabricated in 0.13-mum CMOS and measurement results are demonstrated.     

一种双频段CMOS低噪声放大器

描述了一个可同时处理输入信号在937.5 MHz和408 MHz频段,应用于数字对讲机射频前端的双频段CMOS低噪声放大器(LNA)。所有的输入输出都被匹配到50Ω。芯片采用0.18μmCMOS工艺制造。仿真结果显示,在1.5 V供电电压下,937.5 MHz时,LNA的噪声系数、功率增益和偏置电流分别为0.92 dB、19.0 dB和6.0 mA;408 MHz时,分别为0.72 dB、20.9 dB和3.0 mA。据笔者所知,这是首个可以处理频率低至408 MHz信号的双频段CMOS低噪声放大器。     

一种高增益宽带共栅CMOS电流模跨阻放大器

文章提出了一种高增益宽带共栅CMOS电流模跨阻放大器，从理论上对电路进行了分析。采用0．5μm CMOS工艺进行HSPICE仿真，结果表明，该电路结构能达到57dBΩ跨阻增益，1．5GHz带宽，6．4pA／sqrt(Hz)等效输入总电流噪声；在输入电流为200pA时，其输出电压的动态摆幅达到220mV，功耗仅为76mW。