氧化对SOI基SiGe薄膜残余应变弛豫的影响

研究了氧化对外延在SOI衬底上的SiGe薄膜的残余应变弛豫过程的影响.通过对SiGe薄膜采用不同工艺的氧化,从而了解不同氧化条件对SOI基SiGe薄膜的应变弛豫过程的影响.氧化将会促使SiGe薄膜中的Ge原子扩散到SOI材料的顶层硅中.而SiGe薄膜的残余应变弛豫过程将会与Ge原子的扩散过程同时进行,通过对SiGe薄膜和SOI顶层硅中位错分布的分析发现:在氧化过程中,SiGe薄膜和SOI衬底之间存在一个应力传递的过程.     

Si间隔层对利用低温Si缓冲层生长高弛豫SiGe层的影响

利用低温生长Si缓冲层与Si间隔层相结合的方法生长高弛豫SiGe层,研究了Si间隔层在其中的作用. 利用化学腐蚀和光学显微镜,观察了不同外延层厚度处位错的腐蚀图样. 研究了不同温度下生长的Si间隔层对SiGe外延层中位错形成、传播及其对应变弛豫的影响. 结果表明Si间隔层的引入,显著改变了外延层中位错的形成和传播,进而使得样品表面形貌也呈现出较大的差异.     

Si间隔层对利用低温Si缓冲层生长高弛豫SiGe层的影响

利用低温生长Si缓冲层与Si间隔层相结合的方法生长高弛豫SiGe层,研究了Si间隔层在其中的作用.利用化学腐蚀和光学显微镜,观察了不同外延层厚度处位错的腐蚀图样.研究了不同温度下生长的Si间隔层对SiGe外延层中位错形成、传播及其对应变弛豫的影响.结果表明Si间隔层的引入,显著改变了外延层中位错的形成和传播,进而使得样品表面形貌也呈现出较大的差异.     

Si间隔层对利用低温Si缓冲层生长高弛豫SiGe层的影响

利用低温生长Si缓冲层与Si间隔层相结合的方法生长高弛豫SiGe层,研究了Si间隔层在其中的作用.利用化学腐蚀和光学显微镜,观察了不同外延层厚度处位错的腐蚀图样.研究了不同温度下生长的Si间隔层对SiGe外延层中位错形成、传播及其对应变弛豫的影响.结果表明Si间隔层的引入,显著改变了外延层中位错的形成和传播,进而使得样品表面形貌也呈现出较大的差异.     

弛豫SiGe衬底上SiGe/Si Ⅱ型量子阱

采用 UHV / CVD系统 ,在 Si衬底上生长了具有渐变 Si1 - x Gex 缓冲层结构的弛豫 Si0 .76 Ge0 .2 4虚衬底和 5个周期的 Si0 .76 Ge0 .2 4/ Si多量子阱 .在渐变 Si1 - x Gex 缓冲层生长过程中引入原位退火 ,消除了残余应力 ,抑制了后续生长的 Si Ge中的位错成核 .透射电子显微照片显示 ,位错被有效地限制在组份渐变缓冲层内 ,而 Si Ge上层和 Si Ge/Si量子阱是无位错的 .在样品的 PL 谱中 ,观察到跃迁能量为 0 .96 1e V的 型量子阱的无声子参与 (NP)发光峰 .由于 型量子阱中电子和空穴不在空间同一位置 ,较高光功率激发下引起的高浓度载流子导致能带弯曲严重 .NP峰随激发功率增加向高能方向移动 ,在一定激发条件下 ,电子跃迁或隧穿至弛豫 Si Ge层弯曲的导带底后与处于同一位置的空穴复合发光 ,所以 NP峰积分强度随光激发功率先增加后减小     

弛豫SiGe衬底上SiGe/SiⅡ型量子阱

采用 UHV / CVD系统 ,在 Si衬底上生长了具有渐变 Si1 - x Gex 缓冲层结构的弛豫 Si0 .76 Ge0 .2 4虚衬底和 5个周期的 Si0 .76 Ge0 .2 4/ Si多量子阱 .在渐变 Si1 - x Gex 缓冲层生长过程中引入原位退火 ,消除了残余应力 ,抑制了后续生长的 Si Ge中的位错成核 .透射电子显微照片显示 ,位错被有效地限制在组份渐变缓冲层内 ,而 Si Ge上层和 Si Ge/Si量子阱是无位错的 .在样品的 PL 谱中 ,观察到跃迁能量为 0 .96 1e V的 型量子阱的无声子参与 (NP)发光峰 .由于 型量子阱中电子和空穴不在空间同一位置 ,较高光功率激发下引起的高浓度载流子导致能带弯     

弛豫SiGe衬底上SiGe/Si Ⅱ型量子阱

采用UHV/CVD系统,在Si衬底上生长了具有渐变Si1-xGex缓冲层结构的弛豫Si0.76Ge0.24虚衬底和5个周期的Si0.76Ge0.24/Si多量子阱.在渐变Si1-xGex缓冲层生长过程中引入原位退火,消除了残余应力,抑制了后续生长的SiGe中的位错成核.透射电子显微照片显示,位错被有效地限制在组份渐变缓冲层内,而SiGe上层和SiGe/Si量子阱是无位错的.在样品的PL谱中,观察到跃迁能量为0.961eV的Ⅱ型量子阱的无声子参与(NP)发光峰.由于Ⅱ型量子阱中电子和空穴不在空间同一位置,较高光功率激发下引起的高浓度载流子导致能带弯曲严重.NP峰随激发功率增加向高能方向移动,在一定激发条件下,电子跃迁或隧穿至弛豫SiGe层弯曲的导带底后与处于同一位置的空穴复合发光,所以NP峰积分强度随光激发功率先增加后减小.     

离子注入诱导下制备薄的高弛豫SiGe

通过离子注人硅衬底,在表面引入缺陷,诱导超高真空化学气相沉积(UHV/CVD)生长的外延SiGe发生驰豫,以制备薄的高弛豫SiGe.利用微区Raman和Tapping AFM技术,对所生长的SiGe材料进行了表征.结果表明,上述方法能够制备厚度为100nm、弛豫度达94%的大面积(直径为125mm)均匀SiGe材料.然而,相同条件下,如果高能离子直接辐照SiGe层,将极大地损坏外延材料的晶体结构,得到多晶SiGe.此外,还通过选择性腐蚀外层SiGe的实验,对相关微观机制进行了研究.     

离子注入诱导下制备薄的高弛豫SiGe

通过离子注入硅衬底,在表面引入缺陷,诱导超高真空化学气相沉积（UHV/CVD）生长的外延SiGe发生驰豫,以制备薄的高弛豫SiGe. 利用微区Raman和Tapping AFM技术,对所生长的SiGe材料进行了表征. 结果表明,上述方法能够制备厚度为100nm、弛豫度达94%的大面积（直径为125mm）均匀SiGe材料. 然而,相同条件下,如果高能离子直接辐照SiGe层,将极大地损坏外延材料的晶体结构,得到多晶SiGe. 此外,还通过选择性腐蚀外层SiGe的实验,对相关微观机制进行了研究.     

SiGe与SOI：模拟／混合信号电路的先导技术

ＳｉＧｅ与ＳＯＩ：模拟／混合信号电路的先导技术亦然摘编在当今众多模拟／混合信号工艺技术中，又出现两种新兴技术。这就是正在崭露头角的硅－锗异质结双极晶体管（ＳｉＧｅＨＢＴ）工艺和已经在大多数先进的互补双极（ＣＢ）工艺中大显身手的绝缘体上硅（ＳＯＩ）技术...     

Compliant substrates: A comparative study of the relaxation mechanisms of strained films bonded to high and low viscosity oxides

Relaxation of compressively strained heteroepitaxial Si_0.7Ge_0.3 films bonded to high and low viscosity glass compliant layers was investigated. These structures were formed by transferring Si_0.7Ge_0.3 films to Si substrates covered with thermal SiO₂ and borophosphorosilicate glass (BPSG) films. Relaxation was studied through thermal annealing experiments. For the low viscosity BPSG, relaxation was observed near 800°C and was accompanied by buckling of the Si_0.7Ge_0.3 film. At this temperature, no change in the Si_0.7Ge_0.3 film bonded to thermal SiO₂ was observed, and through this comparison relaxation on BPSG is interpreted as the result of viscous flow of the glass. Finally, film buckling was successfully avoided by patterning the strained films into small areas prior to annealing, and is an indication that film expansion must be considered for elastic strain relaxation on compliant media.     

The Influence of Strain Relaxation on the Electrical Properties of Submicron Si/SiGe Resonant-Tunneling Diodes

Resonant tunneling devices (RTDs) and resonant tunneling transistors (RTTs) are possible building blocks with increased functionality of future microelectronic circuits. These quantum devices can be made in the Si/SiGe system, which is compatible with Si technology. We have fabricated Si/SiGe RTDs with submicron lateral dimensions and have studied their electrical properties. In particular, we have measured the size-dependence of these properties in p-type mesa-etched dots and wires. We find that the I-V characteristics can be strongly influenced by strain relaxation at the side walls of the heterostructure. Here we study this effect of strain relaxation on the quantum-well subbands. The lateral dimensions of the devices ranged from 10 m down to 230 nm. It was found that both the subband-edge energy and the kinetic energy associated with the in-plane motion of holes are strongly influenced by the size and shape of the device. This result is explained by analyzing the effect of strain relaxation on the valence band for the two geometries.     

SiGe沟道SOI CMOS的设计及模拟

在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 ,PMOSFET增加得更多一些     

全部耗尽SOI SiGe HBT集电结渡越时间模型研究

研究了与CMOS兼容的SOI SiGe HBT结构。首先,分析了SOI SiGe HBT与传统SiGe HBT在结构上的不同之处。然后,针对新结构的全部耗尽工作模式,建立了考虑电流效应的集电结渡越时间模型。最后,讨论了渡越时间与集电区掺杂浓度、集电结电压、传输电流的关系,并与传统器件的渡越时间进行了比较。该渡越时间模型的建立为SOI SiGe HBT特征频率的设计与优化提供了理论基础。     

应用400℃低温Si技术制备应变Si沟道pMOSFET

在利用分子束外延方法制备SiGe pMOSFET中引入了低温Si技术.通过在Si缓冲层和SiGe层之间加入低温Si层,提高了SiGe层的弛豫度.当Ge主分为20%时,利用低温Si技术生长的弛豫Si1-xGex层的厚度由UHVCVD制备所需的数微米降至400nm以内,AFM测试表明其表面均方粗糙度(RMS)小于1.02nm.器件测试表明,与相同制备过程的体硅pMOSFET相比,空穴迁移率最大提高了25%.     

Strain relaxation mechanisms in Si1−xGex layers grown by solid-phase epitaxy: Influence of the layer composition and growth temperature

The influence of the composition and growth temperature on the strain and defect structure of Si_1−xGe_x layers of 0.21≤x≤0.34 grown on (001) Si wafers by solid phase epitaxy is presented. The strain in the layers was measured by Raman spectroscopy and Rutherford backscattering spectrometry/channeling angular scans. The defects were analyzed using high resolution electron microscopy. Three different relaxation mechanisms have been identified and characterized. The first mechanism occurs at the layer-substrate interface of the samples by the introduction of isolated defects. It is found to be thermally activated with an activation energy of E_a=0.16 eV and a prefactor that depends on the Gecontent of the layer. This mechanism produces partial relaxation of the layers and hinders the growth of fully strained layers. The second relaxation mechanism emerges at a distance from the interface which depends on the stress in the crystallized portion of the layer. In this case, the strain relaxation is caused by stacking faults that nucleate when they are energetically feasible and propagate toward the surface of the sample during growth. At low growth temperatures, the defects are confined to the upper part of the epitaxial layers at a distance from the interface that agrees with the theoretical predictions based on the equilibrium critical layer thickness. The third relaxation mechanism is introduced at high growth temperature and is based on the gliding of the stacking faults toward the layer-substrate interface. As a result of this mechanism, the stress in the layers is reduced compared to the stress in the layers grown at lower temperatures and approaches the equilibrium value corresponding to the total layer thickness. This behavior indicates that the layers grown at low temperature, where the stacking faults are confined to the upper part, are to some extent metastable.     

应用400℃低温Si技术制备应变Si沟道pMOSFET

在利用分子束外延方法制备Si Ge p MOSFET中引入了低温Si技术.通过在Si缓冲层和Si Ge层之间加入低温Si层,提高了Si Ge层的弛豫度.当Ge主分为2 0 %时,利用低温Si技术生长的弛豫Si1 - x Gex 层的厚度由UHVCVD制备所需的数微米降至4 0 0 nm以内,AFM测试表明其表面均方粗糙度(RMS)小于1.0 2 nm.器件测试表明,与相同制备过程的体硅p MOSFET相比,空穴迁移率最大提高了2 5 % .     

SiGe共振腔增强型探测器的制备

利用SOI材料的埋层二氧化硅的自停止特性,成功制作了具有高反射底镜的共振腔增强型SiGe探测器.底镜沉积于EPW腐蚀液腐蚀形成的背孔内,在1.2～1.5μm范围内,反射率高达99%.探测器的共振峰在1.344μm,光响应为1.2mA/W.与普通结构的探测器相比,文中所报道的探测器光响应有8倍的增强.