氧化对SOI基SiGe薄膜残余应变弛豫的影响

研究了氧化对外延在SOI衬底上的SiGe薄膜的残余应变弛豫过程的影响.通过对SiGe薄膜采用不同工艺的氧化,从而了解不同氧化条件对SOI基SiGe薄膜的应变弛豫过程的影响.氧化将会促使SiGe薄膜中的Ge原子扩散到SOI材料的顶层硅中.而SiGe薄膜的残余应变弛豫过程将会与Ge原子的扩散过程同时进行,通过对SiGe薄膜和SOI顶层硅中位错分布的分析发现:在氧化过程中,SiGe薄膜和SOI衬底之间存在一个应力传递的过程.     

干法氧化制备SiGe弛豫缓冲层及其表征

SiGe弛豫缓冲层是高性能Si基光电子与微电子器件集成的理想平台.通过1000℃干法氧化组分均匀的应变Si0.88Ge0.12层,在Si衬底上制备了表面Ge组分大于0.3,弛豫度大于95%,位错密度小于1.2×105cm-2的Ge组分渐变SiGe弛豫缓冲层.通过对不同氧化时间的样品的表征,分析了氧化过程中SiGe应变弛豫的主要机制.     

干法氧化制备SiGe弛豫缓冲层及其表征

SiGe弛豫缓冲层是高性能Si基光电子与微电子器件集成的理想平台.通过1000℃干法氧化组分均匀的应变Si0.88Ge0.12层,在Si衬底上制备了表面Ge组分大于0.3,弛豫度大于95%,位错密度小于1.2×105cm-2的Ge组分渐变SiGe弛豫缓冲层.通过对不同氧化时间的样品的表征,分析了氧化过程中SiGe应变弛豫的主要机制.     

GSMBE外延生长SGOI材料的退火行为

在SIMOX SOI超薄硅衬底上外延生长了高质量SiGe合金薄膜来制备SGOI(SiGe on insulator)样品,并研究了其在1050℃氧化气氛中的高温退火行为.用Raman,DCXRD,RBS和光学显微镜等分析手段对SGOI样品在退火前后的性能进行了表征.分析结果表明:SGOI样品表面的穿透位错密度约为5×105cm-2;高温退火处理可以促进SGOI样品中异质外延生长SiGe合金薄膜的弛豫化和超薄Si夹层向SiGe合金薄膜的转化,进一步提高SiGe薄膜的晶体质量,并且有助于获得高Ge组分的SGOI材料.     

GSMBE外延生长SGOI材料的退火行为

在SIMOX SOI超薄硅衬底上外延生长了高质量SiGe合金薄膜来制备SGOI(SiGe on insulator)样品，并研究了其在1050℃氧化气氛中的高温退火行为．用Raman，DCXRD，RBS和光学显微镜等分析手段对SGOI样品在退火前后的性能进行了表征．分析结果表明：SGOI样品表面的穿透位错密度约为5e５ｃｍ－２；高温退火处理可以促进SGOI样品中异质外延生长SiGe合金薄膜的弛豫化和超薄Si夹层向SiGe合金薄膜的转化，进一步提高SiGe薄膜的晶体质量，并且有助于获得高Ge组分的SGOI材料．     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术,制备出应变Si/弛豫Si0.9Ge01/渐变组分弛豫SiGe/Si衬底.通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺,有效地降低了表面粗糙度和位错密度.与Ge组分突变相比,采用线性渐变组分后,应变硅材料表面粗糙度从3.07nm减小到0.75nm,位错密度约为5×104 cm-2,表面应变硅层应变度约为0.45%.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术,制备出应变Si/弛豫Si0.9Ge01/渐变组分弛豫SiGe/Si衬底.通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺,有效地降低了表面粗糙度和位错密度.与Ge组分突变相比,采用线性渐变组分后,应变硅材料表面粗糙度从3.07nm减小到0.75nm,位错密度约为5×104 cm-2,表面应变硅层应变度约为0.45%.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术，制备出应变Si/弛豫Si0.9Ge0.1/渐变组分弛豫SiGe/Si衬底. 通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺，有效地降低了表面粗糙度和位错密度.与Ge组分突变相比，采用线性渐变组分后，应变硅材料表面粗糙度从3.07nm减小到0.75nm，位错密度约为5E4cm-2，表面应变硅层应变度约为0.45%.     

纳米CMOS电路的应变Si衬底制备技术

应变硅衬底材料——弛豫SiGe层作为应变硅技术应用的基础,其质量的好坏对应变硅器件性能有致命的影响。综述了近年来用于纳米CMOS电路的各类弛豫SiGe层的制备技术,并对弛豫SiGe层中应变测量技术进行了简单的介绍,以期推动应变硅技术在我国芯片业的应用。     

微区中MBE共度生长SiGe/Si异质结构的应变和退火效应

报道了在Si衬底上微米尺寸的介质膜窗口中,采用分子束外延技术共度生长的Si0.8Ge0.2薄膜的应变及其退火特性. 实验表明,微区生长材料的这些特性,与同一衬底上无边界约束条件下生长的材料相比,有明显的不同.微米尺寸窗口中生长的SiGe/Si材料的应变与窗口尺寸有关,也和窗口的掩膜中的内应力有关.实验还表明,边缘效应对于微区中共度生长的SiGe/Si材料的热稳定性也有显著的影响.在3μm×3μm窗口中共度生长的Si0.8Ge0.2/Si异质结构材料,在950℃高温退火30min后,它的应变弛豫不大于4%.远小于同一衬底上非微区生长材料的应变弛豫.文章还对微区生长材料的这些特性成因进行了探讨.     

Fabrication of thick, high-quality strained SiGe layer on ultra-thin silicon-on-insulator and modeling of film strain

Fabrication of a thick strained SiGe layer on bulk silicon is hampered by the lattice mismatch and difference in the thermal expansion coefficients between Si and SiGe, and a high Ge content leads to severe strain in the SiGe film. When the thickness of the SiGe film is above a critical value (90 nm for 18% Ge), drastic deterioration of the film properties as well as dislocations will result. In comparison, a silicon-on-insulator (SOI) substrate with a thin top Si layer can mitigate the problems and so a thick SiGe layer with high Ge concentration can conceivably be synthesized. In the work reported here, a 110 nm thick high-quality strained Si_0.82Ge_0.18 layer was fabricated on an ultra-thin SOI substrate with a 30 nm top silicon layer using ultra-high vacuum chemical vapor deposition (UHVCVD). The thickness of the SiGe layer is larger than the critical thickness on bulk Si. Cross-sectional transmission electron microscopy (XTEM) reveals that the SiGe layer is dislocation-free and the atoms at the SiGe/Si interface are well aligned, even though X-ray diffraction (XRD) data indicate that the SiGe film is highly strained. The strain factors determined from the XRD and Raman results agree well.     

A study of the oxidation behavior and the postannealing effect in a graded SiGe/Si heterostructure

A study on the dry thermal oxidation of a graded SiGe layer was performed. To reduce the Ge pileup effect during the thermal oxidation, the SiGe layer was deposited with much lower Ge content near the free surface than near the SiGe/Si heterointerface. After dry thermal oxidation at 900°C, the Ge composition in the pileup layer was significantly reduced and strain relaxation by defect formation was prevented due to the graded Ge distribution. To homogenize the Ge distribution between the pileup layer and remaining SiGe layer, the oxidized layers were postannealed. The homogenization is significantly enhanced by strain-induced diffusion, and it was confirmed by uphill diffusion of Ge. This result can propose an alternative oxidation method of strained SiGe/Si heterostructures.     

Pure germanium epitaxial growth on thin strained silicon-germanium graded layers on bulk silicon substrate for high-mobility channel metal-oxide-semiconductor field-effect transistors

We demonstrate epitaxially grown high-quality pure germanium (Ge) on bulk silicon (Si) substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD) without involving growth of thick relaxed SiGe buffer layers. The Ge layer is grown on thin compressively strained SiGe layers with rapidly varying Ge mole fraction on Si substrates resulting in several SiGe interfaces between the Si substrate and the pure Ge layer at the surface. The presence of such interfaces between the Si substrate and the Ge layer results in blocking threading dislocation defects, leading to a defect-free pure Ge epitaxial layer on the top. Results from various material characterization techniques on these grown films are shown. In addition, capacitance-voltage (CV) measurements of metal-oxide-semiconductor (MOS) capacitors fabricated on this structure are also presented, showing that the grown structure is ideal for high-mobility metal-oxide-semiconductor field-effect transistor applications.     

Strain evolution of SiGe-on-insulator fabricated by germanium condensation method with over-oxidation

Strain evolutions of SiGe film during Ge condensation processes of SiGe on silicon-on-insulator were studied in detail with assistance of X-ray diffraction. At the beginning of Ge condensation, SiGe on silicon-on-insulator with low Ge fraction was oxidized at higher temperature of 1150 °C, the strong plastic deformation of buried SiO₂ and Si-Ge intermixing relieved most of the strain in SiGe with increasing Ge fraction. When temperature was reduced to 900 °C for oxidation of SiGe layer with higher Ge fraction, Ge accumulation overmatched Si-Ge inter-diffusion, resulting in non-uniform profile of Ge in SiGe layer. During this period, plastic deformation of buried SiO₂ can be neglected and dislocation gliding plays a significant role in relieving strain in SiGe, which enlarges the surface roughness. The strain in SiGe increases gradually with condensation time for the thickness of SiGe layer reduces close to its critical thickness, even with higher Ge fraction. Intensive over-oxidation of germanium-on-insulator materials was suggested to be effective to fully relax the compressive strain but should be precisely controlled to avoid surface deterioration.     

Ultrathin strained-SOI by stress balance on compliant substrates and FET performance

Ultrathin, strained-silicon-on-insulator (s-SOI) structures without a residual silicon-germanium (SiGe) underlayer have been fabricated using stress balance of bi-layer structures on compliant borophosphorosilicate glass (BPSG). The bi-layer structure consisted of SiGe and silicon films, which were initially pseudomorphically grown on a silicon substrate and then transferred onto BPSG by a wafer bonding and SmartCut process. The viscous flow of the BPSG during a high-temperature anneal then allowed the SiGe/Si bi-layer to laterally coherently expand to reach stress balance, creating tensile strain in the silicon film. No dislocations are required for the process, making it a promising approach for achieving high-quality strained-silicon for device applications. To prevent the diffusion of boron and phosphorus into the silicon from the BPSG, a thin nitride film was inserted between the bi-layer and BPSG to act as a diffusion barrier, so that a lightly doped, sub-10-nm s-SOI layer (0.73% strain) was demonstrated. N-channel MOSFETs fabricated in a 25-nm silicon layer with 0.6% strain showed a mobility enhancement of 50%.     

半导体锗纳米团簇和纳米层的生成与结构研究

我们在硅锗合金衬底上采用氧化等制膜方式生成零维和二维的纳米结构样品，用高精度椭偏仪(HPE)、卢瑟福背散射谱仪(RBS)和高分辨率扫描透射电子显微镜(HR-STEM)测量样品的纳米结构，并采用美国威思康新州立大学开发的Rump模拟软件对卢瑟福背散射谱(RBS)中的CHANNEL谱和RANDoM谱分别进行精细结构模拟，测量并计算出纳米氧化层与锗的纳米薄膜结构分布，并且反馈控制加工过程，优化硅锗半导体材料纳米结构样品的加工条件。我们测量出样品横断面锗纳米团簇和纳米层的PL发光谱。我们在硅锗合金的氧化层表面中首次发现纳米锗量子点组成的几个纳米厚的盖帽膜结构，我们首次提出的生成硅锗纳米结构的优化加工条件的氧化时间和氧化温度匹配公式的理论模型与实验结果拟合得很好。     

CVD生长Si基Si1-x-yGexCy合金层应变的研究

用Raman谱和AES能谱分析了用RTP/VLP-CVD方法生长在Si衬底上的SiGeC合金外延薄膜的应变。结果表明:用RTP/VLP-CVD方法生长的SiGeC合金中掺入的C呈间隙原子或替位原子的形式分布,其中大部分为间隙原子,少量为替位C原子,但是替位C原子的存在有效地调节了SiGeC合金层的应变;另外由于采用乙烯做C源,生长温度较高也使SiGeC合金层的应变部分被弛豫。由于C的掺入,Si基上生长SiGeC合金的应变和相同Ge含量的SiGe合金相比较大大减小,临界厚度大大增加,有利于在Si衬底上生长出达到一定厚度的更高质量的族元素合金半导体材料。     

硅锗合金氧化后生成的锗纳米结构的特性研究

我们将SiGe合金在干氧吹气环境下以不同的温度和不同的时值进行氧化处理，用卢摄福散射仪RBS和高精度椭偏仪HP-ESM测量样品，获得10～80nm厚的硅氧化层和1nm厚的富锗层．新发现快速氧化生成的氧化膜表面有1～2nm厚的锗层．分析了锗纳米结构对应的PL发光谱，注意到锗纳米层对应的541nm波长的尖锐的发光峰和不同尺寸的锗原子团对应的从550～720nm波长的发光带．从量子受限模型和局域密度泛函计算出发。合理地解释了实验的结果．