A Current-Mode DC-DC Buck Converter with High Stability and Fast Dynamic Response

提出了一种高稳定性的电流型DC-DC转换器.首先应用一种新型的电流型转换器的模型推导了控制环路的增益表达式,在分析其环路增益的基础上,提出了一种新颖的控制环路频率补偿的方法,从而使转换器的稳定性不受负载电流和电源电压变化的影响.其次应用这种新的频率补偿方法,使用0.5μm-CMOS工艺设计了一种电流模式的降压型转换器.仿真结果表明,该稳压器具有高度的稳定特性,其稳定性与负载和电源电压无关.并且由于这种新的频率补偿为环路提供了极高的带宽,所以该转换器具有优异的动态响应.其提供的全负载瞬态响应的建立时间小于5μs,过冲电压小于30mV.     

一种新的应用于开关电容DC/DC转换器的补偿电路

采用Chartered 0.35μm CMOS工艺,设计实现了输入电压范围2.7～5.5 V,负载电流高达200mA的降压式开关电容型DC/DC转换器.为了在整个输入电压和负载电流范围内稳定输出电压,并且提高输出电压精确度,在对开关电容转换器环路建模分析后,提出了一个新的应用于开关电容DC/DC转换器的频率补偿电路.该...     

一种基于相加电流模式的DC-DC转换器的研究

给出了相加电流模式控制的DC-DC转换器的小信号模型,讨论了控制环路的频率补偿设计方法,设计了一种采用电流相加模式的DC-DC转换器电路,模拟结果与理论分析相一致,该DC-DC电路响应时间小于40μs,输出精度为20 mV,表明其具有动态响应快、输出精度高等优点.     

应用于前端读出电路的片上LDO设计

为满足辐射探测器前端读出电路对模拟电路稳压器片上集成和快速瞬态时间响应的需求,设计了一种基于0.18μm CMOS工艺的全片上集成LDO。采用大摆幅高增益放大器驱动输出功率管,增大了功率管栅极调节电压摆幅,减小了功率管尺寸和LDO压差电压。该放大器同时增大了LDO的环路增益和对功率管栅极的充放电电流,从而改善了瞬态响应性能。为了不牺牲环路增益带宽和芯片面积,并且保证LDO在整个负载电流区间内保持稳定,提出了一种负载电流分区频率补偿方法。仿真结果表明,在负载电容为200 nF,负载电流范围为0～200 mA时,设计的LDO相位裕度均大于53^o。在相同功率管尺寸情况下,采用大摆幅高增益放大器可以将LDO最大输出电流能力提高到两倍以上。当负载电流从10 mA跳变到200 mA时,LDO输出电压恢复时间小于6.5μs。设计的LDO电路面积为120μm×264μm,满载时电源效率为97.76%,最小压差电压为50 mV。     

电源设计中为何要与环路补偿纠缠不休

在电源设计行业中,工程师有时难以对其电源的控制环路进行补偿,他们设法让环路在极高开关频率下交叉,以试图改善大信号瞬态响应,但最终却是与稳定性问题作斗争。电源设计中最流行的拓扑之一便是峰值电流模式控制。即使这种拓扑比电压模式控制更容易补偿,但一些电源设计人员仍然只能艰难地对电压环路进行补偿。本文的目的是给工程师一些指导,希望能使峰值电流模式控制的电压环路补偿更容易。     

基于动态频率补偿的LDO电路设计

文中提出了一种基于动态频率补偿技术的LDO电路。通过添加电压缓冲器,提高了LDO的环路增益和瞬态响应特性。该电路通过电流镜采样调整管电流,使主极点频率与第三极点频率随负载电流的改变而产生相同倍数的变化,克服了LDO零极点随负载变化而导致环路稳定性变差的问题。文中设计采用中电二十四所HC12.BJT工艺,利用Spectre仿真工具进行仿真,研究了不同负载电流下该LDO的频率特性及其稳定性问题。仿真结果表明,该电路在10 μA~100 mA负载电流的变化范围内,LDO环路的相位裕度保持在50°~70°之间,证明提出的LDO调整器具有良好的稳定性。     

基于阻尼系数控制频率补偿的无电容型LDO设计

基于级间密勒补偿技术,产生一个低频主极点,并通过阻尼系数控制(DFC)单元调节两个次主极点略高于单位增益频率(UGF),使得无电容型LDO开环传递函数中在UGF内只有一个极点,从而保证环路稳定性,同时又优化了系统的动态响应.基于该结构,采用HHNEC 0.25μm CMOS工艺,设计了一个1.8V 100mA的适合SoC应用的无电容型LDO.其电压降为50mV,在50μA到100mA的负载电流范围内,开环传递函数相位裕度高于55度,瞬态电压过冲值低于140mV,负载电流在最大值与最小值之间阶跃变化时,最大恢复时间为3μs,系统静态电流为40μA.     

一种误差放大式压电陶瓷驱动电源的研制

介绍了压电陶瓷驱动电源的特点,研制了一种改进的误差放大式压电陶瓷驱动电源。该驱动电源采用串联型稳压电路生成直流高压,误差反馈控制电压取自受控压电陶瓷上的电压。通过增加反馈电容与隔离电阻来补偿负载电容带来的系统外部极点。实验证明,在3.13μF负载下该驱动电源输出峰值电流可达700mA,动态响应频率可达1kHz,纹波小于20mV,线性度高,稳定性好,结构简单,造价低。     

一种基于ACOT的Buck型开关电源设计

基于自适应恒定导通时间(ACOT)控制方式,设计了一种恒频效果良好的降压型DC-DC转换器。该转换器采用V²COT架构,兼具输出精度高和瞬态响应速度快的特点。采用一种改进的自适应导通时间控制方式,降低了负载电流对开关频率的影响,使转换器在连续导通模式(CCM)下具有良好的开关频率稳定性。基于东部高科0.15μm BCD工艺完成流片,芯片输入电压为4.5～17 V,输出电压为0.76～7 V,最大负载电流为3 A,开关频率为1 MHz。测试结果表明,在CCM下,开关频率随输入电压变化率为2.67 k Hz/V,随负载电流变化率为2.95 k Hz/A,峰值效率达96.43%,输出电压纹波为8.2 m V,负载调整率为0.93%,负载瞬态响应时间小于20μs。     

一种基于电流比较的无基准电压Cap-less LDO

提出了一种基于电流比较的无基准电压型Cap-less LDO。将输出电压转换为电流后与参考电流比较,无需独立的基准电压模块,可降低功耗。在环路中插入了一个带有源反馈补偿网络的误差放大器,可增加环路增益,从而提升精度,在减少片上补偿电容的同时维持宽负载范围内的环路稳定性。该LDO采用65 nm标准CMOS工艺仿真验证,仿真结果显示,当负载电容为100 pF时,静态电流为9.4μA,片上补偿电容仅需0.25 pF,当输出负载在100μA和50 mA之间处切换时,恢复时间小于1μs,带有源反馈LDO的上冲和下冲分别为94 mV和21 mV,和不带有源反馈的LDO相比,上冲和下冲分别减少了28%和79%。     

电流模降压DC-DC内部补偿研究

利用片内补偿实现了一款单片电流模降压型DC-DC变换器。设计的分段线性斜坡补偿电路大大缓解了传统线性方法的过补偿问题,提高了系统响应速度。集成的RC频率补偿结构克服了稳定性对输出负载以及陶瓷输出电容ESR的依赖,简化了设计,节省了PCB面积。芯片基于标准0.5μm CMOS工艺实现,内部补偿实现了良好的环路稳定性,负载调整率以及线性调整率均小于0.4%,400 mA负载阶跃对应输出电压的响应时间小于8μs。同步整流技术使得效率高达94%。     

A current-mode buck DC-DC controller with adaptive on-time control

A current-mode buck DC-DC controller based on adaptive on-time (AOT) control is presented. The on-time is obtained by the techniques of input feedforward and output feedback, and the adaptive control is achieved by a sample-hold and time-ahead circuit. The AOT current-mode control scheme not only obtains excellent transient response speed, but also achieves the independence of loop stability on output capacitor ESR. In addition, the AOT current-mode control does not have subharmonic oscillation phenomenon seen in fixed frequency peak current-mode control, so there is no need of the slope compensation circuit. The auto-skip pulse frequency modulation (PFM) mode improves the conversion efficiency of light load effectively. The controller has been fabricated with UMC 0.6-μm BCD process successfully and the detailed experimental results are shown.     

Robust average current-mode control of multimodule parallel DC-DCPWM converter systems with improved dynamic response

This paper presents a novel average current-mode control (ACC) strategy for the control of multimodule parallel pulsewidth modulation DC-DC converters, which represents a drastic improvement over conventional ACC. This new method consists of the addition of an auxiliary controller into the control loop, besides the current and voltage regulators. The reference-model-based auxiliary controller improves the robustness of the ACC dynamics in buck-derived distributed power systems, preserving loop gain crossover frequency and stability margins over significant changes of the number of connected modules, the load and the line voltage. Moreover, this control scheme shows much better disturbance rejection properties, i.e., closed-loop output impedance and audiosusceptibility, than conventional ACC. From a control theory point of view robust performance is achieved, preserving stability. A multimodule buck prototype has been experimentally tested with different numbers of modules on stream, line, and load conditions, including discontinuous conduction mode. Measurements of the small-signal frequency response of the converter have been carried out, showing the improvement achieved by the proposed control scheme. The empirical large-signal response of the converter under load steps is also shown in order to validate the concept     

A 1500 mA,10 MHz on-time controlled buck converter with ripple compensation and efficiency optimization

正A 1500 mA,10 MHz self-adaptive on-time(SOT) controlled buck DC-DC converter is presented.Both a low-cost ripple compensation scheme(RCS) and a self-adaptive on-time generator(SAOTG) are proposed to solve the system stability and frequency variation problem.Meanwhile a self-adaptive power transistor sizing(SAPTS) technique is used to optimize the efficiency especially with a heavy load.The circuit is implemented in a 2P4M 0.35μm CMOS process.A small external inductor of 0.47μH and a capacitor of 4.7μF are used to lower the cost of the converter and keep the output ripple to less than 10 mV.The measurement results show that the overshoot of the load transient response is 8 mV @ 200 mA step and the dynamic voltage scaling(DVS) performance is a rise of 16μs/V and a fall of 20μs/V.With a SAPTS technique and PFM control,the efficiency is maintained at more than 81%for a load range of 20 to 1500 mA and the peak efficiency reaches 88.43%.     

电流模降压DC-DC大负载低漏失工作研究

对线性斜坡补偿与芯片峰值电流和带载的关系进行了论证,针对大负载低漏失工作,在分段线性斜坡补偿的基础上,提出了电流抵消电路,得到在箝位状态可调节的斜坡电流,延长了电池的使用寿命,利于便携式应用。电路紧凑简洁,易于实现,并在一款额定带载600mA的电流模降压DC-DC变换器中进行了验证,测试结果表明,达到了100%占空比时输出电压2.5V以及3.3V的600mA大负载低漏失工作。     

DCM,FSM,dead time and width controllers for a high frequency high efficiency buck DC-DC converter over a wide load range

This paper presents a width controller,a dead time controller,a discontinuous current mode(DCM) controller and a frequency skipping modulation(FSM) controller for a high frequency high efficiency buck DC-DC converter. To improve the efficiency over a wide load range,especially at high switching frequency,the dead time controller and width controller are applied to enhance the high load efficiency,while the DCM controller and FSM controller are proposed to increase the light load efficiency.The proposed D...     

Design of anti-jamming current-sensing circuit for current-mode buck regulator

A novel anti-jamming integrated CMOS current-sensing circuit for current-mode buck regulators is presented.Based on the widely-used traditional current-sensing structure,anti-jamming performance is improved significantly by adding on-chip capacitors and one-shot circuit.Also the transient response is faster through the introduction of current offset.The circuit iS concise,simple to implement and suits for SoC applications with single power supply.A dual-output current-mode DC-DC buck converter with proposed structure has been fabricated with a 0.5μm CMOS process for validation.In the 2.5-5.5 V input range,the two channels work steadily in the load current range of 0-600 mA.And the measured maximum efficiency is up to 96%.     

A dual-mode fast-transient average-current-mode buck converter without slope-compensation

A dual-mode fast-transient average-current-mode buck converter without slope-compensation is proposed in this paper. The benefits of the average-current-mode are fast-transient response, simple compensation design, and no requirement for slope-compensation, furthermore, that minimizes some power management problems, such as EMI, size, design complexity, and cost. Average-current-mode control employs two loop control methods, an inner loop for current and an outer one for voltage. The proposed buck converter using the current-sensing and average-current-mode control techniques can be stable even if the duty cycle is greater than 50%. Also, adaptively switch between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is operated with high conversion efficiency. Under light load condition, the proposed buck converter enters PFM mode to decrease the output ripple. Even more, switching PWM mode realizes a smooth transition under heavy load condition. Therefore, PFM is used to improve the efficiency at light load. Dual-mode buck converter has high conversion efficiency over a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 μm CMOS 2P4M processes, the total chip area is 1.45×1.11 mm². Maximum output current is 450 mA at the output voltage 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 0.8-2.8 V. Maximum transient response is less than 10 μs. Finally, the theoretical analysis is verified to be correct by simulations and experiments.     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

Fast transient DC–DC converter with adaptive compensation zero technique

This letter is to present an adaptive compensation zero circuit to achieve good transient response in current-mode DC–DC buck converter. The proposed structure introduces an adaptive resistance dynamically adjusted according to the different output load conditions, which achieves an adequate system phase margin. A monolithic DC–DC buck converter using the proposed structure was fabricated with 0.35 μm CMOS process. Measurement results show that the transient undershoot/overshoot voltage and the recovery time do not exceed 60 mV and 20 μs for a load current variation from 0 to 1 A.