2D Threshold-Voltage Model for High-k Gate-Dielectric MOSFETs

给出包括栅电介质与耗尽层区域的边界条件和二维沟道电势分布.根据这个电势分布,得出高k栅介质MOSFET的阈值电压模型,模型中考虑短沟道效应和高k栅介质的边缘场效应.模型模拟结果和实验结果能够很好地符合.通过和一个准二维模型的结果相比较,表明该模型更准确.另外,还详细讨论了影响高k栅电介质MOSFET阈值电压的一些因素.     

小尺寸堆栈高k栅介质GaAs nMOSFET阈值电压模型

通过求解沟道的二维泊松方程,建立了小尺寸高k栅介质GaAs MOSFET的阈值电压模型．模型包括了短沟道效应、漏致势垒降低效应和量子效应．模拟结果与TCAD仿真结果符合较好,证实了模型的正确性和实用性．利用该模型,分析了堆栈高k栅介质结构及其物理参数对阈值电压漂移的影响以及阈值电压的温度特性．结果表明,堆栈栅介质结构能有效抑制边缘场和DIBL效应,改善MOSFET的阈值特性和温度特性;未考虑量子效应的模型过高估计了温度对阈值电压的影响。     

双栅肖特基源漏MOSFET的阈值电压模型

通过求解泊松方程得到了双栅肖特基势垒MOSFET的解析模型. 这个解析模型包括整个沟道的准二维电势分布和适用于短沟双栅肖特基势垒MOSFET的阈值电压模型.数值模拟器ISE DESSIS验证了模型结果.     

双栅肖特基源漏MOSFET的阈值电压模型

通过求解泊松方程得到了双栅肖特基势垒MOSFET的解析模型. 这个解析模型包括整个沟道的准二维电势分布和适用于短沟双栅肖特基势垒MOSFET的阈值电压模型.数值模拟器ISE DESSIS验证了模型结果.     

高k栅介质MOSFET电特性的模拟分析

对高k栅介质MOSFET栅极漏电进行研究 ,确定栅介质的厚度 ,然后使用PISCES Ⅱ模拟器对高k栅介质MOSFET的阈值电压、亚阈斜率和Idsat/Ioff进行了详细的分析研究。通过对不同k值的MOSFET栅极漏电、阈值电压、亚阈斜率和Idsat/Ioff的综合考虑 ,得出选用k <5 0且Tk/L≤ 0 .2的栅介质能获得优良的小尺寸MOSFET电性能。     

三栅MOSFET阈值电压模型

根据三栅(TG)MOSFET二维数值模拟的结果,分析了TG MOSFET中的电势分布,得出了在硅体与掩埋层接触面的中心线上的电势随栅压变化的关系;通过数学推导,给出了基于物理模型的阈值电压的解析表达式;并由此讨论了多晶硅栅掺杂浓度、硅体中掺杂浓度、硅体的宽度和高度以及栅氧化层厚度对阈值电压的影响;得出在TG MOSFET器件的阈值电压设计时,应主要考虑多晶硅栅掺杂浓度、硅体中掺杂浓度和硅体的宽度等参数的结论。     

An Analytical Threshold Voltage Model for Fully Depleted SOI MOSFETs

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

全耗尽SOI MOSFETs阈值电压解析模型

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

双栅掺杂隔离肖特基MOSFET的解析模型

通过考虑肖特基势垒降低效应求解三段连续的二维泊松方程,建立了双栅掺杂隔离肖特基MOSFET亚阈值区全沟道连续的电势模型。在该电势模型的基础上,推导了阈值电压模型和漏致势垒降低效应的表达式;研究了掺杂隔离区域不同掺杂浓度下的沟道电势分布,分析了沟道长度和厚度对短沟道效应的影响。结果表明,掺杂隔离区域能改善肖特基MOSFET的电学特性;对于短沟道双栅掺杂隔离肖特基MOSFET,适当减小沟道宽度能有效抑制短沟道效应。     

Modeling of Gate Tunneling Current for Nanoscale MOSFETs with High-k Gate Stacks

介绍了一种纳米MOSFET(场效应管)栅电流的统一模型,该模型基于Schrodinger-Poisson方程自洽全量子数值解,特别适用于高k栅介质和多层高k栅介质纳米MOSFET.运用该方法计算了各种结构和材料高k介质的MOSFET栅极电流,并对pMOSFET和nMOSFET高k栅结构进行了分析比较.模拟得出栅极电流与实验结果符合,而得出的优化氮含量有待实验证实.     

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

A 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.     

Influence of sidewall spacer on threshold voltage of MOSFET with high-k gate dielectric

In this paper, an analytical expression of the gate-dielectric fringing-potential distribution is derived for high-k gate-dielectric MOSFET through a conformal-mapping transformation method for the first time. Based on the fringing-potential distribution, the threshold-voltage model of the MOSFET is improved, and the influence of sidewall spacer on the threshold voltage is discussed in detail. Calculated results indicate that low-k sidewall spacer can alleviate the fringing-field effect.     

A 2D threshold-voltage model for small MOSFET with quantum-mechanical effects

A threshold condition different from the classical one is proposed for MOSFET with quantum effects, and is based on self-consistent numerical solution of the Schrödinger’s and Poisson’s equations. Furthermore, an accurate 1D threshold-voltage model including polysilicon-depletion effects is built by experimental fitting. Simulated results exhibit good agreement with measurement data. Based on this 1D model, a 2D quantum-modified threshold-voltage model for small MOSFET is developed by solving the quasi-2D Poisson’s equation and taking short-channel effects and quantum-mechanical effects into consideration. The model can also be used for deep-submicron MOSFET with high-k gate-dielectric and reasonable design of device parameters.     

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D(source/drain) region.It is found that an optimal source/drain-to-gate non-overlapped and high-A:spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering(DIBL) characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.     

Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.