SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

SOI 动态阈值MOS 研究进展

随着器件尺寸的不断缩小,传统MOS器件遇到工作电压和阈值电压难以等比例缩小的难题,以至于降低电路性能,而工作在低压低功耗领域的SOI DTMOS可以有效地解决这个问题。本文介绍了四种类型的SOI DTMOS器件．其中着重论述了栅体直接连接DTMOS、双栅DTMOS和栅体肖特基接触DTMOS的工作原理和性能．具体分析了优化器件性能的五种方案,探讨了SOI DTMOS存在的优势和不足。最后指出,具有出色性能的SOI DTMOS必将在未来的移动通讯和SOC等低压低功耗电路中占有一席之地。     

SOI动态阈值MOS器件结构改进

传统SOI DTMOS器件固有的较大体电阻和体电容严重影响电路的速度特性,这也是阻碍SOI DTMOS器件应用于大规模集成电路的最主要原因之一.有人提出通过增大硅膜厚度的方法减小器件体电阻,但随之而来的寄生体电容的增大严重退化了器件特性.为了解决这个问题,提出了一种SOI DTMOS新结构,该器件可以分别优化结深和硅膜的厚度,从而获得较小的寄生电容和体电阻.同时,考虑到沟道宽度对体电阻的影响,将该结构进一步优化,形成侧向栅-体连接的器件结构.ISE-TCAD器件模拟结果表明,较之传统SOI DTMOS器件,该结构的本征延时和电路延时具有明显优势.     

50nm SOI-DTMOS器件的性能

利用二维器件模拟软件ISE对5 0nm沟道长度下SOI DTMOS器件性能进行了研究,并与常规结构的SOI器件作了比较.结果表明,在5 0nm沟长下,SOI DTMOS器件性能远远优于常规SOI器件.SOI DTMOS器件具有更好的亚阈值特性,其亚阈值泄漏电流比常规SOI器件小2～3个数量级,从而使其具有更低的静态功耗.同时,SOI DTMOS器件较高的驱动电流保证了管子的工作速度,并且较常规SOI器件能更有效地抑制短沟道器件的穿通效应、DIBL及SCE效应,从而保证了在尺寸进一步减小的情况下管子的性能.对SOI DTMOS器件的物理机制进行了初步分析,揭示了其性能远优于常规结构的物理本质     

130nm PDSOI DTMOS体延迟研究

研究了基于IBM 8RF 130 nm工艺部分耗尽绝缘体上Si(PDSOI)动态阈值晶体管(DTMOS)体电阻、体电容以及体电阻和体电容乘积(体延迟)随Si膜厚度和器件宽度的变化.结果表明,Si膜厚度减小会导致体阻增大、体电容减小,但是体电阻和体电容的乘积却明显增大.Si膜厚度从200 nm减小到80nm,体延迟增加将近两个数量级.器件宽度增加使得体电阻和体电容都明显增大,DTMOS电路延迟也因此指数递增.推导出了PDSOI DTMOS的延迟模型,为SOI DTMOS器件设计提供了参考.     

1200V/100A高温大电流4H-SiC JBS器件的研制

基于SiC结势垒肖特基(JBS)二极管工作原理及其电流/电场均衡分布理论,采用高温大电流单芯片设计技术及大尺寸芯片加工技术,研制了1 200 V/100 A高温大电流4H-SiCJBS二极管.该器件采用优化的材料结构、有源区结构和终端结构,有效提高了器件的载流子输运能力.测试结果表明,当正向导通压降为1.60 V时,其正向电流密度达247 A/cm2(以芯片面积计算).在测试温度25和200℃时,当正向电流为100 A时,正向导通压降分别为1.64和2.50 V;当反向电压为1 200 V时,反向漏电流分别小于50和200μA.动态特性测试结果表明,器件的反向恢复特性良好.器件均通过100次温度循环、168 h的高温高湿高反偏(H3TRB)和高温反偏可靠性试验,显示出优良的鲁棒性.器件的成品率达70％以上.     

采用新的抬高源漏工艺技术制作的全耗尽SOI CMOS器件和电路

采用新的工艺技术,成功研制了具有抬高源漏结构的薄膜全耗尽SOI CMOS器件.详细阐述了其中的关键工艺技术.器件具有接近理想的亚阈值特性,nMOSFETs和pMOSFETs的亚阈值斜率分别为65和69mV/dec.采用抬高源漏结构的1.2μm nMOSFETs的饱和电流提高了32%,pMOSFETs的饱和电流提高了24%.在3V工作电压下101级环形振荡器电路的单级门延迟为75ps.     

SOI DTMOS温度特性研究

对比研究了20 μm/0.35 μm的SOI(绝缘体上硅)普通MOS和DTMOS(动态阈值MOS)的温度特性.从20～125℃,普通MOS驱动电流减小了12.2%,而DTMOS驱动电流增大了65.3%.SOI DTMOS降低了垂直沟道方向的电场,减少了载流子表面散射,因此阈值电压随温度减小占主导,驱动电流随着温度升高而增大.SOl DTMOS优秀的温度特性,使之非常适合于低压、低功耗、高温应用.     

具有超高耐压(>1200V)的薄埋氧层BPL SOI LDMOS(英文)

为了在薄埋氧层SOI衬底上实现超高耐压LDMOS铺平道路,提出了一种具有P埋层(BPL)的薄埋氧层SOI LDMOS 结构,耐压1200V以上.该BPL SOI LDMOS在传统SOI LDMOS的埋氧层和N型漂移区之间引入了一个P型埋层.当器件正向截止时,N型漂移区与P埋层之间的反偏PN结将承担器件的绝大部分纵向压降.采用2维数值仿真工具Silvaco TCAD对BPL SOI LDMOS进行虚拟制造和器件仿真,结果表明该结构采用适当的参数既能实现1 280 V的耐压,将BOL减薄到几百纳米以下又可以改善其热特性.     

0.5μm SOI CMOS器件和电路

研究了0.5μm SOI CMOS器件和电路,开发出成套的0.5μm SOI CMOS工艺.经过工艺投片,获得了性能良好的器件和电路,其中当工作电压为3V时,0.5μm 101级环振单级延迟为42ps.同时,对部分耗尽SOI器件特性,如“浮体”效应、“kink”效应和反常亚阈值特性进行了讨论.     

Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

Improved analysis of low frequency noise in dynamic threshold MOS/SOI transistors

In this paper, low-frequency noise (LFN) in N- and P-channel dynamic-threshold (DT) MOSFETs on Unibond substrate (SOI) is thoroughly investigated and, especially, an improved formulation of classical McWhorter’s noise model is proposed. In order to confirm our approach, an experimental comparison between body tied and DTMOS on SOI substrate has been achieved in terms of LFN behaviour. Furthermore, two different types of DTMOS transistors have been used: with and without current limiter. The LFN in DTMOS is analysed in ohmic and saturation regimes and the impact of the use of a current limiter (clamping transistor) is thoroughly analysed. An explanation based on floating body effect inducing excess noise is also proposed.     

A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V     

Impacts of gate structure on dynamic threshold SOI nMOSFETs

The effects of different substrate-contact structures (T-gate and H-gate) dynamic threshold voltage silicon-on-insulator (SOI) nMOSFETs (DTMOS) have been investigated. It is found that H-gate structure devices have higher driving current than T-gate under DTMOS-mode operation. This is because H-gate SOI devices have larger body effect factor (/spl gamma/), inducing a lager reduction of threshold voltage. Besides, it is found that drain-induced-barrier-lowering (DIBL) is dramatically reduced for both T-gate and H-gate structure devices when devices are operated under DTMOS-mode.     

On the power dissipation in dynamic threshold silicon-on-insulatorCMOS inverter

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V     

绝缘体上硅动态阈值nMOSFETs特性研究

基于绝缘体上硅技术,提出并研制动态阈值nMOSFETs结构.阐述了动态阈值nMOSFETs的工作原理.动态阈值nMOSFETs的阈值电压从VBS=0 V时的580 mV动态变化到VBS=0.6 V时的220 mV,但是这种优势并没有以增加漏电流为代价.因此动态阈值nMOSFETs的驱动能力较之浮体nMOSFETs在低压情况下,更具有优势.工作电压为0.6 V时,动态阈值nMOSFETs的驱动能力是浮体的25.5倍,0.7 V时为12倍.而且浮体nMOSFETs中的浮体效应,诸如Kink效应,反常亚阈值斜率和击穿电压降低等,均被动态阈值nMOSFETs结构有效抑制.     

Complimentary single-electron/hole action of nanoscale SOI CMOS transistors

We propose a new device structure for room-temperature single-electron/hole transistors based on nanosize narrow-width fully depleted silicon-on-insulator (SOI) CMOS transistors. The floating body of SOI MOSFETs can become a Coulomb island, whose single charging energy is more than 30 meV, as the gate length and width of MOSFETs is less than 10 nm. As SOI MOSFETs are biased at accumulation, single-electron, or hole tunnels, are sent, one by one, from the source to the floating body and then to the drain via Zener tunneling process. N-channel SOI MOSFETs can have the functions of single-electron transistors (n-SETs) while p-channel MOSFETs can have the functions of single-hole transistors (p-SETs). SOI MOSFETs still behave as typical MOSFETs when biased at inversion. There is a gate voltage margin of 0.9 V to separate Coulomb blockade oscillations from CMOS normal operation.     

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

The authors study the dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness and show a performance improvement for decreasing SOI thickness. The inverse subthreshold slopes S extracted from the experiments are compared with simulations and an analytical approximation. Excellent agreement between experiment, simulation, and analytical approximation is found, which shows that S scales approximately as the square root of the gate oxide and the SOI thickness. In addition, the authors study the impact of the SOI thickness on the variation of the threshold voltage V/sub th/ of SOI SB-MOSFETs and find a nonmonotonic behavior of V/sub th/. The results show that to avoid large threshold voltage variations and achieve high-performance devices, the gate oxide thickness should be as small as possible, and the SOI thickness should be /spl sim/ 3 nm.