应用于2Mb/s GMSK调制的CMOS低功耗全差分Sigma-Delta频率综合器

设计了应用于GMSK调制,工作在2.4GHz,CMOS全差分的∑-△频率综合器.调制器中采用预补偿的分数N锁相环.推导了Ⅱ型三阶锁相环的传输函数,并指出影响环路传输函数的重要参数.介绍了校准重要的环路参数的方法.锁相环设计中采用差分调节的LC压控振荡器和全差分的电荷泵.设计的电路利用0.18μm 1P6M CMOS工艺进行仿真.由于锁相环的组成模块中采用了低功耗设计,锁相环的功耗仅为11mW左右,调制器的数据率达到2Mb/s.     

基于Matlab的三阶电荷泵锁相环的设计与仿真

在分析电荷泵锁相环基本原理的基础上,给出了三级电荷泵锁相环的线性相位模型以及三级电荷泵锁相环的开环和闭环传输函数,结合具体的设计实例利用三级电荷泵锁相环的环路传输函数在MATLAB中对该锁相环进行了系统级设计,最后在SIMULINK中建立了该三级电荷泵锁相环的行为模型,分析系统的建立时间和频率响应等特性.该模型不但可以...     

2-GHz CMOS锁相环时钟发生器研究与设计

采用包含预充电通路,自适应偏置的压控振荡器,设计了一种2-GHz锁相环时钟发生器,并用0.18μm混合信号CMOS工艺实现.分析了环路参数对锁相环输出噪声影响,并对环路参数进行优化.1.8V电源电压下2GHz时钟的rms抖动,peak-peak抖动的测试结果分别为7.27ps,37.5ps,功耗为42mW.     

5Gb/s 0.25μm CMOS限幅放大器

给出了一个90 0 MHz CMOS锁相环/频率综合器的设计,设计中采用了电流可变电荷泵及具有初始化电路的环路滤波器.电荷泵电流对温度与电源电压变化的影响不敏感,同时电流的大小可通过外部控制信号进行切换控制而改变.因此,锁相环的特性,诸如环路带宽等,也可通过电流的改变而改变.采用具有初始化电路的环路滤波器可提高锁相环的启动速度.另外采用了多模频率除法器以实现频率合成的功能.该电路采用0 .18μm、1.8V、1P6 M标准数字CMOS工艺实现.     

900MHz CMOS锁相环/频率综合器

给出了一个900MHz CMOS锁相环/频率综合器的设计,设计中采用了电流可变电荷泵及具有初始化电路的环路滤波器.电荷泵电流对温度与电源电压变化的影响不敏感,同时电流的大小可通过外部控制信号进行切换控制而改变.因此,锁相环的特性,诸如环路带宽等,也可通过电流的改变而改变.采用具有初始化电路的环路滤波器可提高锁相环的启动速度.另外采用了多模频率除法器以实现频率合成的功能.该电路采用0.18μm、1.8V、1P6M标准数字CMOS工艺实现.     

锁相环MSK调制器的性能研究

本文研究一种锁相环MSK调制器的性能。文中详细分析了AFC环路非线性产生相位拖尾的机理及对系统性能的影响。计算机模拟结果表明,这种相位拖尾引入的系统信噪比恶化量,在用相干解调时最大,鉴频解调时居中,而差分解调时最小。最后给出了一个工作于1.5 GHz频段的锁相环MSK调制器的硬件设计及实现。     

小数频率合成器噪声传函及动态特性建模仿真

对采用Δ-Σ小数分频频率合成器(Δ-Σ PLL)中离散采样行为进行了深入研究,提出了混合信号系统的传输函数表达式,并将该表达式运用在现有的锁相环时域模型之上,获得了环路中量化噪声以及压控振荡器(VCO)的噪声传输函数模型.此外,论述了一种简化计算方法用于获得三阶锁相环动态参数,并对Δ-Σ PLL噪声和闭环带宽的折衷进行了建模与仿真.     

基于锁相环的高稳定性斩光器的设计

描述了一种采用锁相环来稳定斩光频率的设计方法.将斩光盘组件代替锁相环中的压控振荡器,就可以构成锁相电机控制系统,并由此得到数学模型.通过对其传输函数的分析,可以依次作出环路的奈奎斯特图、根轨迹图和波特图.通过奈奎斯特图能够了解环路的稳定条件;通过根轨迹图能进一步看到当改变环路参数时环路闭环极点在复平面上的移动情况;波特图则显示出环路的稳定余量.合理选择环路参数能保证环路的可靠锁定及良好的动态性能.经测试,应用本方案,斩光器的斩光频率能达到晶体级的稳定性(优于100×10-6/℃),相位抖动小于1%,能极好地满足相关检测技术的要求.     

低相位噪声和低参考杂散CMOS锁相环的优化设计与实现

基于Simulink建立的CMOS电荷泵锁相环的动态模型,对电荷泵锁相环的环路参数与环路稳定性的关系进行了仿真与分析,根据分析结果确定了4GHz锁相环的环路参数,并围绕低相位噪声和低参考杂散设计了锁相环各单元电路结构。该锁相环采用SMIC 0.18m CMOS工艺进行了流片,芯片面积为675μm×700μm。测试的VCO在控制电压为0.3~1.5V时,振荡频率为3.98~4.3GHz;当分频比为1036,参考信号频率为4MHz,锁定状态下锁相环的相位噪声测量值为-120.5dBc/Hz@100kHz及-127.5dBc/Hz@1MHz;电路参考杂散约为-70dB,整体性能优良。     

一种单环Δ-Σ调制器的全数字实现

针对无线人体局域网(WBAN),采用TSMC 0.18μm CMOS工艺,对3阶单环结构Δ-Σ调制器进行了优化设计和全数字实现。实验结果表明,在Δ-Σ调制器中使用Qn方法实现对浮点小数的定点化,优化后的结构能够在运算精度、器件尺寸及功耗上达到平衡。该研究工作可以为实现全数字小数锁相环提供重要的理论及设计参考。     

Design of an Improved CMOS Phase/Frequency Detector

A complementary metal oxide semiconductor (CMOS) phase/frequency detector (PFD) is presented. An improved CMOS D-type master-slave flip-flop is described and adopted in the PFD. Higher speed and lower power operation is attributed to the reduced node capacitance. Charge-sharing phenomena are circumvented in the proposed flip-flop and PFD. The maximum frequency of operation of the PFD is analytically studied. Device-sizing equations, based upon a first-order approximation, for the PFD are derived. The proposed PFD shows improvements in both phase and frequency sensitivities at high operating frequencies. HSPICE simulations of a phase-locked loop (PLL) employing the improved PFD demonstrate a faster frequency acquisition. The PLL simulations also verify that the maximum operating frequency of the PFD is in agreement with our analytical results.     

A 1-GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY

The design procedure of an 1-GHz phase-locked loop (PLL)-based frequency synthesizer used in IEEE 1394b physical (PHY) system is presented in this paper. The PLL’s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL’s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 m complementary metal oxide semiconductor (CMOS) technology.     

A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider

The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-/spl mu/m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz over the whole tuning range.     

A Low-Noise and Low-Power Frequency Synthesizer Using Offset Phase-Locked Loop in 0.13-$mu{rm m}$ CMOS

In this letter, a fractional-N frequency synthesizer based on an offset phase-locked loop (OPLL) architecture is presented. The proposed synthesizer achieves low-noise as the two low-pass filters that are inherent in the OPLL highly suppresses the quantization noise from the delta-sigma modulator. In addition, it consumes low power by employing charge-recycling technique in the sub-PLL. A prototype synthesizer implemented in 0.13 $mu{rm m}$ CMOS process achieves 9 dB of noise reduction compared to a conventional PLL while consuming 3.2 mW of power.      

Optimization of phase-locked loop performance in data recoverysystems

Optimized design conditions are presented for a phase-locked loop (PLL) used as a functional block in data recovery systems with the primary function of timing recovery. A mathematical model is presented which takes into account the nonlinear and discrete-time nature of the PLL when used in data recovery applications. Performance attributes for these systems such as acquisition, tracking, and noise are considered. A systematic design procedure is presented which permits quantitative trade-offs among these performance attributes. The validation of the mathematical model and the systematic design procedure on a practical circuit implementation in CMOS technology is described     

一种低功耗低噪声大带宽锁相环的设计

本文描述了一种低功耗低噪声大带宽锁相环路(PLL),给出了锁相环各组成单元模块的设计思路及电路结构。设计采用CMOS0.35μm工艺。压控振荡器的电源电压为3V,工作在900MHz-2GHz,典型功耗为3.4mW。电路占芯片上面积为450X400μm。     

A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessorapplications

A phase-locked loop (PLL) for CMOS UltraSPARC microprocessor applications uses a loop filter referenced to a quiet power supply and achieves measured clock period jitter of ±25 ps at 360 MHz. The fully integrated CMOS PLL uses a charge-pump phase/frequency detector, a single-capacitor loop filter, and a feedforward error correction architecture. Loop characteristics are analyzed and verified by measurements. The measured sensitivity of clock period jitter to supply voltage is 2.6 ps/100 mv over an analog supply-voltage range of 1.6-2.1 V; the measured output operating frequency range is 8.5-660 MHz. Fabricated in an area of 310×280 μm² in a 0.25-μm CMOS process, the PLL dissipates 25 mW from a 1.9-V supply     

带有自适应频率校准单元的26~41 GHz锁相环

采用45 nm SOI CMOS工艺,设计了一种带有自适应频率校准单元的26~41 GHz 锁相环。该锁相环包括输入缓冲器、鉴频鉴相器、电荷泵、环路滤波器、压控振荡器、高速时钟选通器、分频器和频率数字校准单元。采用了基于双LC-VCO的整数分频锁相环,使用了自适应频率选择的数字校准算法,使得锁相环能在不同参考时钟下自适应地调整工作频率范围。仿真结果表明,该锁相环的输出频率能够连续覆盖26~41 GHz。输出频率为26 GHz时,相位噪声为-103 dBc/Hz@10 MHz,功耗为34.64 mW。输出频率为41 GHz时,相位噪声为-96 dBc/Hz@10 MHz,功耗为35.44 mW。     

用90nm CMOS数字工艺实现的低抖动时钟锁相环设计

用90nmCMOS数字工艺设计实现了一个低抖动的时钟锁相环.锁相环不需要"模拟"的电阻和电容,采用金属间的寄生电容作为环路滤波器的电容.测试结果显示,锁相环锁定在1.989GHz时的均方抖动为3.7977ps,周期峰峰值抖动为31.225ps,核心功耗约为9mW.锁相环可稳定输出的频率范围为125MHz到2.7GHz.     

用90nm CMOS数字工艺实现的低抖动时钟锁相环设计

用90nmCMOS数字工艺设计实现了一个低抖动的时钟锁相环.锁相环不需要"模拟"的电阻和电容,采用金属间的寄生电容作为环路滤波器的电容.测试结果显示,锁相环锁定在1.989GHz时的均方抖动为3.7977ps,周期峰峰值抖动为31.225ps,核心功耗约为9mW.锁相环可稳定输出的频率范围为125MHz到2.7GHz.