A 162GHz Self-Aligned InP/InGaAs Heterojunction Bipolar Transistor

报道了发射极自对准的InP基异质结双极型晶体管.在集电极电流Ic=34.2mA的条件下,发射极面积为0.8μm×12μm的InP HBT截止频率fT为162GHz,最大振荡频率fmax为52GHz,最大直流增益为120,偏移电压为0.10V,击穿电压BVCEO达到3.8V(Ic=0.1μA).这种器件非常适合在高速低功耗方面的应用,例如OEIC接收机以及模拟数字转换器.     

f＝210GHz的超高速InP/InGaAs单异质结晶体管

成功地将Polyimide钝化平坦化工艺应用于InP/InGaAs单异质结晶体管制作工艺中.在Vce=1.1V,Ic=33.5mA的偏置条件下,发射极尺寸为1.4μm×1.5μm的器件,其ft达到210GHz.这种器件非常适合高速低功耗方面的应用,例如超高速数模混合电路以及光学通信系统等.     

f=210GHz的超高速InP/InGaAs单异质结晶体管

成功地将Polyimide钝化平坦化工艺应用于InP/InGaAs单异质结晶体管制作工艺中.在Vce=1.1V,Ic=33.5mA的偏置条件下,发射极尺寸为1.4μm×1.5μm的器件,其ft达到210GHz.这种器件非常适合高速低功耗方面的应用,例如超高速数模混合电路以及光学通信系统等.     

fT=140GHz,fmax=200GHz的超高速InP DHBT

InP/InGaAs/InP DHBT具有频带宽、电流驱动能力强、线性好、相位噪声低和阈值电压一致性好等优点成为研究热点。通过优化外延材料结构设计和采用四元InGaAsP缓变层消除集电结电流阻塞效应;改进发射极-基极自对准工艺和集电区台面侧向腐蚀工艺,降低Rb和Cbc乘积;优化PI钝化工艺和空气桥互联等工艺,实现了发射极面积为2μm×10μm的自对准InP/InGaAs/InP DHBT器件,其直流增益β约为25,击穿电压BVCEO≥7 V@10μA,在VCE=4 V,Ic=10 mA下,截止频率fT=140 GHz,最高振荡频率fmax=200 GHz,优于同一外延片上的非自对准InP DHB器件,该器件将可应用于高速光通信和微波毫米波通信。     

采用新的T型发射极技术的自对准InP/GaInAs单异质结双极晶体管的性能

研究了一种采用新的T型发射极技术的自对准InP/GaInAs单异质结双极晶体管.采用了U型发射极图形结构、选择性湿法腐蚀、LEU以及空气桥等技术,成功制作了U型发射极尺寸为2μm×12μm的器件.该器件的共射直流增益达到170,残余电压约为0.2V,膝点电压仅为0.5V,而击穿电压超过了2V.器件的截止频率达到85GHz,最大振荡频率为72GHz,这些特性使此类器件更适合于低压、低功耗及高频方面的应用.     

Performance of a Self-Aligned InP/GaInAs SHBT with a Novel T-Shaped Emitter

研究了一种采用新的T型发射极技术的自对准InP/GaInAs单异质结双极晶体管.采用了U型发射极图形结构、选择性湿法腐蚀、LEU以及空气桥等技术,成功制作了U型发射极尺寸为2μm×12μm的器件.该器件的共射直流增益达到170,残余电压约为0.2V,膝点电压仅为0.5V,而击穿电压超过了2V.器件的截止频率达到85GHz,最大振荡频率为72GHz,这些特性使此类器件更适合于低压、低功耗及高频方面的应用.     

InP/InGaAs/InP双异质结双极晶体管技术研究

介绍了InP/InGaAs/InP双异质结双极晶体管(DHBT)材料生长、器件结构与设计、制作工艺和性能测试以及在振荡器中的应用等方面的研究.采用发射极-基极自对准工艺制作了InP/InGaAs/InP DHBT器件,发射极尺寸为1.5μm×10μm的器件小电流直流增益β约25,集电极-发射极击穿电压BVCEO≥10V,截止频率,ft和最高振荡频率,fmax分别为50和55GHz;     

InP/InGaAs/InP双异质结双极晶体管技术研究

介绍了InP/InGaAs/InP双异质结双极晶体管(DHBT)材料生长、器件结构与设计、制作工艺和性能测试以及在振荡器中的应用等方面的研究.采用发射极-基极自对准工艺制作了InP/InGaAs/InP DHBT器件,发射极尺寸为1.5μm×10μm的器件小电流直流增益β约25,集电极-发射极击穿电压BVCEO≥10V,截止频率,ft和最高振荡频率,fmax分别为50和55GHz;     

MBE生长的InP DHBT的性能

报道了一种自对准InP/InGaAs 双异质结双极晶体管的器件性能.成功制作了U型发射极尺寸为2μm×12μm的器件,其峰值共射直流增益超过300,残余电压约为0.16V,膝点电压仅为0.6V,而击穿电压约为6V.器件的截至频率达到80GHz,最大震荡频率为40GHz.这些特性使此类器件更适合于低压、低功耗及高频方面的应用.     

MBE生长的InP DHBT的性能

报道了一种自对准InP/InGaAs 双异质结双极晶体管的器件性能.成功制作了U型发射极尺寸为2μm×12μm的器件,其峰值共射直流增益超过300,残余电压约为0.16V,膝点电压仅为0.6V,而击穿电压约为6V.器件的截至频率达到80GHz,最大震荡频率为40GHz.这些特性使此类器件更适合于低压、低功耗及高频方面的应用.     

高性能六边形发射极InGaP/GaAs异质结双极型晶体管

六边形发射极的自对准InGaP/GaAs异质结具有优异的直流和微波性能.采用发射极面积为2μm×10μm的异质结双极型晶体管,VCE偏移电压小于150mV,膝点电压为0.5V(IC=16mA),BVCEO大于9V,BVCBO大于14V,特征频率高达92GHz,最高振荡频率达到105GHz.这些优异的性能预示着InGaP/GaAs HBT在超高速数字电路和微波功率放大领域具有广阔的应用前景.     

低偏置电压工作的自对准InGaP/GaAs功率异质结双极晶体管

介绍L波段、低偏置电压下工作的自对准InGaP/GaAs功率异质结双极晶体管的研制.在晶体管制作过程中采用了发射极-基极金属自对准、空气桥以及减薄等工艺改善其功率特性.功率测试结果显示:当器件工作在AB类,工作频率为2GHz,集电极偏置电压仅为3V时,尺寸为2×(3μm×15μm)×12的功率管获得了最大输出功率为23dBm,最大功率附加效率为45%,线性增益为10dB的良好性能.     

高增益异质结光电晶体管的研制

利用液相外延技术研制出高增益InGaAsP/InP异质结光电晶体管(HPT)。入射光波长为1.256μm时,实现直流光增益为88.9,微分光增益为148,光谱响应范围为0.85～1.3μm。在外偏电压小于4V时暗电流小于10nA。     

A novel approach for focusing electron beams using low-cost ceramicgrid [field emitter arrays]

A low-cost ceramic grid was used as a stand-alone focusing electrode in field emitter arrays to obtain high brightness and small electron beam size. The ceramic grid with an array of 200-μm holes was made from DuPont 591 with low-cost equipment. Beam size is controllable by the voltage applied to the focusing grid. Light intensity profiles were measured and analyzed. The full width at half maximum (FWHM) of the light profile excited by electron emission from 30-μm wide field emitter arrays is 60 μm at 5000 V with 6 mm anode-cathode separation. At an anode voltage of 2000 V and gate voltage of 55 V, focusing is optimized at a focusing voltage of 30 V. Arc-free operation at 10 kV was achieved, thereby promoting improved phosphor efficiency. This focusing approach may lead to improve lifetimes for field emission displays and other vacuum microelectronic devices by significantly increasing the total vacuum volume and providing a means for improved getter utilization     

4H–SiC BJTs with current gain of 110

4H–SiC BJTs with a common emitter current gain of 110 have been demonstrated. The high current gain was attributed to a thin base of 0.25 μm which reduces the carrier recombination in the base region. The device open base breakdown voltage (BV_CEO) of 270 V was much less than the open emitter breakdown voltage (BV_CBO) of 1560 V due to the emitter leakage current multiplication from the high current gain by “transistor action” of BJTs. The device has shown minimal gain degradation after electrical stress at high current density of >200 A/cm²up to 25 h.     

A new fabrication process of field emitter arrays with submicrongate apertures using local oxidation of silicon

The field emitter arrays with submicron gate apertures for low voltage operation have been successfully fabricated by modifying the conventional Spindt process. The key element of the new process is forming the gate insulator by local oxidation of silicon, resulting in the reduction of the gate hole size due to the lateral encroachment of oxide. The gate hole diameter of 0.55 μm has been obtained from the original mask pattern size of 1.55 μm. An anode current of 0.1 μA per emitter is measured at the gate voltage of about 53 V, while the gate current is less than 0.3% of the anode current. To obtain the same current level from a Spindt-type emitter with the same gate hole diameter as the mask pattern size, a gate bias of about 82 V is needed     

SiGe HBT超宽带低噪声放大器设计

采用ADS软件设计并仿真了一种应用于UWB标准的低噪声放大器。该低噪声放大器基于JAZZ 0.35μmSiGe工艺,工作带宽为3.1～10.6GHz。电路的输入极采用共发射极结构,利用反馈电感来进行输入匹配,第二级采用达林顿结构对信号提供合适的增益。使用ADS2006软件进行设计、优化和仿真。仿真结果显示,在3.1～10.6GHz带宽内,放大器的电源电压在3.3V时,噪声系数低于2.5dB,增益大于24dB,功耗为28mV,输出三阶交调为17dBm。     

Process and device performance of a high-speed double poly-Sibipolar technology using borosenic-poly process with coupling-baseimplant

Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process resolves both the channeling and shadowing effects of a sidewall-oxided spacer during the base boron implantation. The process also minimizes crystal defects generated during the emitter and base implantations. The coupling-base boron implant significantly improves a wide variation in the emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage current gain, cutoff frequency, or ECL gate delay time. A deep trench isolation with 4-μm depth and 1.2-μm width reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The application of self-aligned titanium silicide technology to form polysilicon resistors without holes and to reduce the sheet resistance of the emitter and collector polysilicon electrodes to 1 Ω/square is discussed