A Low Noise,1.25Gb/s Front-End Amplifier for Optical Receivers

设计并实现了一种基于TSMC 0.25μm CMOS工艺的低噪声、1.25Gb/s和124dBΩ的光接收机前端放大器.跨阻放大器设计采用了有源电感并联峰化和噪声优化技术,克服了CMOS光检测器大寄生电容造成的带宽不够的问题.测试结果表明,在2pF的寄生电容下,前端放大器工作速率达到了1.25Gb/s,在光功率为-17dBm的光信号输入下得到了清晰的眼图.芯片采用3.3V电压供电,功耗为122mW,差分输出电压幅度为660mV.     

12路并行30Gb/s 0.18μm CMOS光接收前端放大器

给出了一个采用TSMC 0.18μm CMOS工艺设计并实现的12路30Gb/s并行光接收前端放大器.电路设计采用RGC结构和噪声优化技术,克服了CMOS光检测器大寄生电容造成的带宽不够的问题.测试结果表明,在2pF的寄生电容下单信道传输速率达到了2.5Gb/s,在0.8mVpp输入下得到了清晰的眼图.提出了一种同时采用p+保护环(PGR)、n+保护环(NGR)和深n阱(DNW)的并行放大器隔离结构,有效地抑制了并行放大器之间的串扰,减小了放大器之间的衬底耦合噪声.测量结果表明,这种结构与PGR和PGR+NGR相比,在1GHz时放大器之间的隔离度分别提高了29.2和8.1dB,在2GHz时放大器之间的隔离度分别提高了8.1和2.5dB.芯片采用1.8V电源供电,单路前端放大器的功耗为85mW,12路总功耗约为1W.     

A 12-Channel,30Gb/s,0.18μm CMOS Front-End Amplifier for Parallel Optic-Fiber Receivers

给出了一个采用TSMC 0.18μm CMOS工艺设计并实现的12路30Gb/s并行光接收前端放大器.电路设计采用RGC结构和噪声优化技术,克服了CMOS光检测器大寄生电容造成的带宽不够的问题.测试结果表明,在2pF的寄生电容下单信道传输速率达到了2.5Gb/s,在0.8mVpp输入下得到了清晰的眼图.提出了一种同时采用p 保护环(PGR)、n 保护环(NGR)和深n阱(DNW)的并行放大器隔离结构,有效地抑制了并行放大器之间的串扰,减小了放大器之间的衬底耦合噪声.测量结果表明,这种结构与PGR和PGR NGR相比,在1GHz时放大器之间的隔离度分别提高了29.2和8.1dB,在2GHz时放大器之间的隔离度分别提高了8.1和2.5dB.芯片采用1.8V电源供电,单路前端放大器的功耗为85mW,12路总功耗约为1W.     

2.5Gb/s宽动态范围光接收机前端放大电路设计

基于UMC 0.18μm CMOS工艺,设计了一种2Gb/s传输速率的宽动态范围光接收机前端放大电路。采用对数放大器来增大接收机的输入动态范围,前置放大器采用差分共源跨阻放大器,并使用有源电感做负载来增大带宽。实验结果表明:该接收机前端电路的增益为80dB,3dB带宽为2.3GHz,2.5Gb/s输出眼图良好,输入动态范围为60dB(1μA～1mA)。     

2.5Gb/s 0.35μm CMOS光接收机前置放大器设计

采用0.35 μm CMOS工艺设计并实现了用于SDH系统STM-16(2.5 Gb/s)速率级光接收机前置放大器.此放大器采用+5 V电源电压,中频增益为73 dBΩ,3 dB带宽为2.2 GHz.核面积为0.15 mm×0.20 mm.     

12×10Gb/s CMOS并行光接收机前置放大器阵列设计

采用SMIC 0.18 μm CMOS工艺,设计了一种12路并行、每路工作速率为10Gb/s的光接收机前置放大器阵列,应用于高速芯片间的光互连.整个电路通过1.8V电压供电,采用RGC结构和有源电感并联峰化技术,单路中频跨阻增益为47.1dBΩ,-3dB带宽为8.9GHz.芯片工作时总的传输速率为120Gb/s.     

基于0.18μm CMOS工艺2.5Gb/s宽动态范围光接收机前端放大电路设计

基于0.18μm CMOS工艺设计了适用于2.5Gb/s传输速率的宽动态范围光接收机前端放大电路（包括前置放大器和限幅放大器）.前置放大器采用了RGC输入级的跨阻放大器,并且应用了消直流电路和自动增益控制电路扩展输入动态范围.限幅放大器采用了按比例缩小尺寸、并联峰化和带有有源负反馈的Cherry-Hooper放大器等方法扩展带宽.仿真结果表明：前端放大电路的中频增益为116dBΩ,-3dB带宽为2.13GHz,输入信号动态范围为40dB（0.01～1mA）.     

10Gb/s 0.18μm CMOS光接收机前端放大电路

介绍了利用TSMC 0.18μm CMON工艺设计的应用于SDH STM-64速率级(10Gb/s)光接收机前端放大电路。该电路由前置放大器和作为主放大器的限幅放大器构成,其中前置放大器采用RGC形式的互阻放大器实现,限幅放大器采用改进的Cherry—Hooper结构。模拟结果表明该电路可以工作在10Gb/s速率上。     

0.18μm CMOS 10Gb/s光接收机限幅放大器

利用TSMC 0.18μm CMOS工艺设计了应用于SDH系统STM-64(10 Gb/s)速率级光接收机中的限幅放大器.该放大器采用了改进的Cherry-Hooper结构以获得高的增益带宽积,从而保证限幅放大器在10Gb/s以及更高的速率上工作.测试结果表明,此限幅放大器在10Gb/s速率上,输入动态范围为42dB(3.2mV~500mV),50Ω负载上的输出限幅在250mV,小信号输入时的最高工作速率为12Gb/s.限幅放大器采用1.8 V电源供电,功耗110mW.芯片的面积为0.7mm×0.9mm.     

1.25Gb/s CMOS高灵敏度宽动态范围跨阻放大器

采用0.35μm CMOS工艺设计并实现了一种新的应用于1.25Gb/s光纤通信接收机的高灵敏度、宽动态范围跨阻放大器电路。引入电流注入技术提高输入管跨导、优化噪声性能、提高灵敏度。自带直流反馈实现直流消除功能,同时采用自动增益控制机制,提高动态范围。仿真结果表明,该电路具有82.02dBΩ的跨阻增益、872.7MHz的带宽、23.74kHz的低频截止频率,输入等效噪声电流为4.08pA/Hz(1/2),最大输入光信号为+3dBm(2mA),在3.3V的电源电压下,芯片功耗为43.4mW。     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 kOmega and a differential output swing of 520 mV_pp with for input spanning from to . The measured integrated input-referred noise is 3.3muA_rms. The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s 2³¹ - 1 PRBS input, the recovered clock jitter is and 0.7ps_rms. The retimed data exhibits 13.3 ps_pp jitter with BER . Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply.     

Three-stage burst-mode transimpedance amplifier in deep-sub-/spl mu/m CMOS technology

A transimpedance amplifier, designed in a digital 120-nm CMOS technology, used as preamplifier for optical burst-mode receivers in passive optical networks is presented. A wide optical input power range of 27 dB can be handled with a variable transimpedance without stability problems by varying the open-loop gain by a factor of 115. Noise and stability analysis of the optical receiver are presented. Sensitivities of - 31.3 dBm at 622 Mb/s and - 28.6 dBm at 1.25 Gb/s with a bit error ratio of 10/sup -10/ and a pseudorandom bit stream of 2/sup 31/-1 are achieved with a power consumption of 88.5 mW.     

应用于10Gb/s光接收机的全差分CMOS跨阻前置电路设计

设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 mVpp的差分电压信号。该全差分前置放大电路采用0.18 m CMOS工艺进行设计,当光电二极管电容为250 fF时,该光接收机前置放大电路的跨阻增益为92 dB,-3 dB带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 pA/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 mW,限幅放大器功耗为80 mW,输出缓冲器功耗为40 mW,其芯片面积为800 m1 700 m。     

A 0.18 μm CMOS TIA Plus Limiting Amplifier with a 5.3 GHz Overall Bandwidth for Fiber Optic Communications

A shunt series feedback transimpedance amplifier (TIA), based on a current amplifier using a zero–pole cancellation, followed by a 6 stages limiting amplifier (LA), proves to be suitable as receiver front-end for a 8 Gb/s communications over fiber optic. The front-end is realized with a 0.18 μm CMOS technology, and shows the following performances: the TIA has a 50 dBΩ transimpedance gain and 5.5 GHz bandwidth, the LA has a 46 dB gain and 7.9 GHz bandwidth. The differential voltage swing at the output is 300 mV. The total power consumption is 112 mW.     

A fully integrated CMOS receiver front-end for optic GigabitEthernet

A fully integrated fiber-optic receiver chip in a CMOS technology is presented. The design was done in a low-cost mixed-signal analog pure CMOS technology with 0.35-μm gate length. It incorporates every building block needed for standard fiber-optic receiver application, e.g., transimpedance amplifier, postamplifier, signal detect, and several control circuits. The chip works without any external components, such as capacitors usually needed to ensure the broadband operation down to several tens of kilohertz. Three designs were processed for typical data applications between 155 Mb/s and 1.25 Gb/s. The difference in the designs can be created by changing only one metal mask and programming some bandwidth and noise-relevant components on the chip. The results in sensitivity, dynamic range, and other behaviors are fully compliant with the relevant standards, such as SONET or IEEE 802.3 (Gigabit Ethernet) and future IEEE 1394 plastic optical fiber (POF) communication     

Compact 2.5 Gb/s Burst‐Mode Receiver with Optimum APD Gain for XG‐PON1 and GPON Applications

This letter presents a compact 2.5 Gb/s burst‐mode receiver using the first reported monolithic amplifier IC developed with 0.25 …m SiGe BiCMOS technology. With optimum avalanche photodiode gain, the receiver module can obtain a fast response, high sensitivity and wide dynamic range, satisfying the overhead timing and various power specifications for a 2.5 Gb/s next‐generation passive optical network (PON), as well as a legacy 1.25 Gb/s PON in the upstream.