动态连接库的应用

开发大型的应用软件系统时通常都采用模块化的编程方式,将应用程序分成很多模块,这些模块分别完成相对独立的功能,它们彼此协作构成整个软件系统。在编程过程中可能有一些模块的功能较为通用,在构建其它软件系统时仍然可以使用。于是Windows系统平台提供了一种有效的编程和运行环境,你可以将独立的程序模块创建为较小的动态连接库-DLL(Dynamic Link Librarires)文件,并可对它们单独编译和测试。国家无线电监测中心组织开发的“全国无线电管理地理信息系统(Oracle版)”提供了功能强大的二次软件开发包“MGS图形软件开发包”,该软件开发包采用了DLL开发模式,将相应的功能封装到不同的DLL中。开放了这些DLL的出口函数并提供了“全国无     

C^＋＋ Builder中DLL的创建及调用

DLL是一个能被应用程序和其他的DLL调用的过程与函数的集合体,它包含公共代码或资源.由于DLL使用内存共享技术,在某些地方Windows也给了DLL一些更高的权限,因而DLL中可以实现一些一般程序所不能实现的功能.同时,DLL还为不同语言间的代码共享提供了一条捷径.因而DLL在编程时应用较为广泛.在此介绍了在Borland C++ Builder 6开发平台中创建及调用其自身的DLL,以及如何调用由Visual C++ 6.0所生成的DLL.     

Win32环境下动态链接库（DLL）编程

介绍在Win32环境下用Visual C＋＋进行动态链接库（DLL）编程方法,以将独立的程序模块创建为较小的DLL（Dynamic Linkable Library)文件,并可对它们单独编译和测试。增加了程序设计人员在Windows环境中开发软件的灵活性,使软件与Windowe系统达到了优化结合。     

VC++中DLL的实现及其在数据采集控制中的应用

介绍了VC 中实现DLL编程的基本方法及其实现的三种基本形式，并且分析了DLL技术的优缺点。以一个实际的数据采集与控制程序为例，编制了相应的数据采集程序，阐述了VC 中DLL。DLL编程的基本流程和技术。     

基于Windows 的DLL编程及应用

介绍了DLL技术在windows编程中的基本方法及应用，并结合程序代码介绍了DLL程序直接内存访问和端口I／O读写的具体实现过程。     

如何充分利用VFP的外部库资源

利用VISAL FOXPRO进行编程时，可使用的三种类型的外部库资源ActiveX控件（.OCX文件），动态链接库（．DLL文件），Visual Fox Pro外部库（．FLL文件）的基本原理和使用方法。     

在VisualFoxporo程序中调用外部资源

本文给出在利用VISAL FOXPRO进行编程时，可使用的三种类型的外部库资源ActiveX控件（.OCX文件），动态链接库（.DLL)文件，Visual FoxPro外部库（.FLL文件）的基本原理和使用方法。     

基于COM技术的网络通信组件的开发

COM(组件对象模型)为基于组件的应用提供了一种技术标准.文中介绍了COM技术,并通过实例介绍了如何使用活动模板库(ATL)工具创建基于COM的网络通信组件.该组件为实现网络通信提供了新的方法,以动态链接库(DLL)形式提供给用户, 具有语言无关性.该开发方法有利于发挥各种编程语言的优势和提高编程效率,从而使应用程序的编写和维护更加容易,充分体现了软件复用的程序设计思想.     

Windows环境下动态链接库(DLL)程序设计

介绍了在Windows平台下动态链接库的工作机制，详细讨论了使用动态链接库的编程方法，并给出了一个DLL主函数的例子。     

在Visual Foxpro程序中调用外部资源

本文给出在利用VISALFOXPRO进行编程时 ,可使用的三种类型的外部库资源ActiveX控件 (.OCX文件 ) ,动态链接库 (.DLL文件 ) ,VisualFoxPro外部库 (.FLL文件 )的基本原理和使用方法     

Design of tracking loop with dirty templates for UWB communication systems

Maintaining satisfactory synchronization between transmitter and receiver is one of the major challenges in carrying out highly efficient ultra-wideband (UWB) communications. For tracking purposes, the delay-locked loop (DLL) concept is applied. The DLL could be considered as a fundamental tracking technique for UWB devices. In this paper, the reference signal is generated at the receiver based on an approach called timing with dirty template. This approach promises to improve tracking performance while reducing receiver structure complexity. After the reference template is generated, we derive first-order and second-order DLL designs for UWB systems. Furthermore, we utilize the benefits of time-hopping codes to enhance noise handling ability of the DLL. Finally, the parameters of the proposed DLL will be selected to optimize tracking behavior in the presence of the ambient noise and Doppler effects. Simulation results show tracking performance across various DLL parameter values.     

用0.35μm CMOS工艺实现存储接口单元中的数模混合DLL

论述了一种利用0.35mm、双阱、双层金属、双层多晶硅的CMOS工艺所实现的延迟锁定环(DLL)。该DLL用于RISC处理器中存储接口部件的时钟同步。本文介绍了其应用背景,给出了DLL的系统结构,接着分别介绍了鉴相器、电荷泵以及压控延迟线的电路结构,最后给出相关仿真结果。     

可实现快速锁定的FPGA片内延时锁相环设计

延时锁相环（DLL）是一种基于数字电路实现的时钟管理技术。DLL可用以消除时钟偏斜,对输入时钟进行分频、倍频、移相等操作。文中介绍了FPGA芯片内DLL的结构和设计方案,在其基础上提出可实现快速锁定的延时锁相环OSDLL设计。在SMIC0．25μm工艺下,设计完成OSDLL测试芯片,其工作频率在20-200MHz,锁定时间相比传统架构有大幅降低。     

一种用于DS-CDMA基站的全数字非相干延迟锁相环

本文根据直接序列扩频码分多址(DS-CDMA)系统上行链路伪随机码跟踪的特点,给出并分析一种全数字非相干延迟锁相环 (DLL),该DLL采用了二元鉴相和数字序贯滤波的实现结构。文中推导了多用户环境下环路的数学模型及鉴相误差统计特性,给出了跟踪性能的计算机仿真结果。研究结果表明,本文给出的DLL能以小的复杂度实现良好的跟踪性能,具有较高的应用价值。     

Noncoherent delay-lock tracking loop for chip-interleaving DS SSsystem

A noncoherent delay-lock loop (DLL) is proposed for code tracking in chip-interleaving (CI) direct sequence (DS) spread spectrum (SS) systems. Analyses show that the proposed loop achieves the same code-tracking performance as the traditional noncoherent DLL does for conventional DS SS systems     

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

A 1-Gb/s/pin 512-Mb DDRII SDRAM has been developed using a digital delay-locked loop (DLL) and a slew-rate-controlled output buffer. The digital DLL has a frequency divider for DLL input, performs at an operating frequency of up to 500 MHz at 1.6 V, and provides internal clocking with 50% duty-cycle correction. The DLL has a current-mirror-type interpolator, which enables a resolution as high as 14 ps, needs no standby current, and can operate at voltages as low as 0.8 V. The slew-rate impedance-controlled output buffer circuit reduces the output skew from 107 to 10 ps. This SDRAM was tested using a 0.13-/spl mu/m 126.5-mm/sup 2/ 512-Mb chip.     

Analysis of DLL Jitter due to Voltage-Controlled Delay Line

In this paper we analyze jitter in a delay-locked loop (DLL) due to uncertainties in the voltage-controlled delay line (VCDL). To obtain a closed-form equation for jitter in the DLL, time-domain equations of the DLL are used. The jitter at the intermediate stages of the VCDL and the jitter of a conventional delay cell are analyzed. The simulation results show that the jitter of the DLL due to mismatch of the delay cells is zero at the beginning and end of the VCDL and is highest at the middle of the VCDL. Also, a DLL is designed in TSMC 0.18 μm CMOS technology to show the accuracy of the proposed analytical method.     

Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface

A multi-phase digital delay-locked loop (DLL) capable of a low-jitter feature for DDR memory interface is reported. The DLL repeatedly selects the output clock edge which is closest to the reference clock edge to reduce the total jitter. A test chip was fabricated in a 0.18 mm CMOS process to verify its functionality. The measured RMS and peak-to-peak jitter of the DLL are 6.2 and 20.4 ps, respectively. The power consumption of the DLL is 12 mW from a 1.8 V supply voltage.     

Design-for-testability for embedded delay-locked loops

This paper introduces a new approach to testing a basic analog-only delay-locked loop (DLL) that is embedded in a field-programmable gate array, an application specific integrated circuit, or a system-on-chip (SoC). Part of the DLL circuitry is duplicated and then connected to the DLL in a way that produces a replica of the control voltage. This shadow of the control voltage is used to measure the loop's response to a step in phase. The concept of test construct (TC) gain is introduced as a means of improving detectability. The benefit of the testing approach is demonstrated by injecting defects into the DLL and detecting them through the TC at the observation point.     

A 250-622 MHz deskew and jitter-suppressed clock buffer usingtwo-loop architecture

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-μm CMOS technology is used to fabricate the chip