Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops

This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies [periods of less than 8/spl times/ the delay of a fan-out-4 inverter (FO-4)] and faster frequency acquisition. Prototypes designed in 0.25-/spl mu/m CMOS process exhibit operating frequencies of 1.25 GHz [=1/(8/spl middot/FO-4)] and 1.5 GHz [=1/(6.7/spl middot/FO-4)] for two techniques, respectively, whereas a conventional PFD operates at <1 GHz [=1/(10/spl middot/FO-4)]. The two proposed PFDs achieve a capture range of 1.7/spl times/ and 1.4/spl times/ the conventional design, respectively.     

A novel pulse swallow based frequency divider circuit for a phase-locked loops

In this paper, an analysis of the memory effect in two amplifier-shared switched-capacitor integrators for a discrete-time sigma-delta (\(\varSigma \varDelta\)) modulator is presented. Interaction between the integrators is modeled by feeding an integrator output voltage to another integrator input and vice versa and multiplying by a coefficient depending on DC gain and input parasitic capacitance of the opamp. The model is applied to a second-order \(\varSigma \varDelta\) modulator to analyze how signal and noise transfer functions are altered. The analysis reveals that the magnitude response of the signal transfer function is minimally affected in the low-frequency signal band, whereas that of the noise transfer function can be increased significantly in the signal band, degrading the effectiveness of noise shaping. In relation to the parasitic capacitance at the opamp input, the DC gain required of the opamp is derived quantitatively for a given degradation of modulator dynamic range with respect to different oversampling ratios. Considering leaky integration, which is also caused by the finite opamp DC gain, the DC gain requirement imposed by the memory effect is proved to be more severe than that by leaky integration. Macromodel-based circuit simulation results confirm the accuracy of the proposed model and equations.     

Behavioral modeling phase-locked loops for mixed-mode simulation

Phase-locked Loops(PLLs) are a class of feedback systems with wide range of applications. A PLL in its entirety can be viewed as a closed-loop servosystem, comprised of three major functional subsystems; 1) Phase detectors, 2) Loop filters and 3) Voltage/Current controlled oscillators. The overall characteristics of the phase-locked loop are dependent on the realization of individual subsystems which have mixed analog-digital implementations. In simulating a PLL, one has to deal with the mixed-signal nature of most implementations, as well as the problem of simulating the PLL over a large number of signal cycles. Long simulation run times plague the simulation of a PLL using a conventional simulator, sometimes making such simulation impractical. In the methodology described in this paper, these drawbacks are overcome by the use of behavioral models and a mixed-signal simulation platform. This paper presents a general mixed-mode behavioral simulation methodology and the derivation of behavioral simulation models for various kinds of PLLs. The top-down and bottom-up modeling paradigms are illustrated through the use of examples of actual PLL designs. The simulation models are generated for the AT&T Bell Laboratories mixed analog-digital simulator, ATTSIM.     

Analysis of charge-pump phase-locked loops

In this paper, we present an exact analysis for third-order charge-pump phase-locked loops using state equations. Both the large-signal lock acquisition process and the small-signal linear tracking behavior are described using this analysis. The nonlinear state equations are linearized for the small-signal condition and the z-domain noise transfer functions are derived. A comparison to some of the existing analysis methods such as the impulse-invariant transformation and s-domain analysis is provided. The effect of the loop parameters and the reference frequency on the loop phase margin and stability is analyzed. The analysis is verified using behavioral simulations in MATLAB and SPECTRE.     

Experimental relative frequency stabilization of a set of lasersusing optical phase-locked loops

A relative frequency stabilization technique using optical phase locking of miniature diode pumped Nd:YAG ring lasers is described. The master laser is RF phase modulated with a modulation index up to 7.4, and slave lasers are locked up to 21 master laser sidebands with a frequency stability better than 3 kHz     

Replica compensated linear regulators for supply-regulated phase-locked loops

Supply-regulated phase-locked loops rely upon the VCO voltage regulator to maintain a low sensitivity to supply noise and hence low overall jitter. By analyzing regulator supply rejection, we show that in order to simultaneously meet the bandwidth and low dropout requirements, previous regulator implementations used in supply-regulated PLLs suffer from unfavorable tradeoffs between power supply rejection and power consumption. We therefore propose a compensation technique that places the regulator's amplifier in a local replica feedback loop, stabilizing the regulator by increasing the amplifier bandwidth while lowering its gain. Even though the forward gain of the amplifier is reduced, supply noise affects the replica output in addition to the actual output, and therefore the amplifier's gain to reject supply noise is effectively restored. Analysis shows that for reasonable mismatch between the replica and actual loads, regulator performance is uncompromised, and experimental results from a 90 nm SOI test chip confirm that with the same power consumption, the proposed regulator achieves at least 4 dB higher supply rejection than the previous regulator design. Furthermore, simulations show that if not for other supply rejection-limiting components in the PLL, the supply rejection improvement of the proposed regulator is greater than 15 dB.     

An analysis of charge-pump phase-locked loops

The charge pump phase-locked loops with a digital sequential phase frequency detector are analyzed using linear and nonlinear models. Nonlinear analytical maps are derived. The stability analysis results agree with linear analysis results, with higher order corrections. The effects of the loop delay are also discussed.     

On phase-locked loops and Kalman filters

Driessen (1994) and Christiansen (1994) independently showed that for a specific dynamic model, the proportional-integral phase-locked loop (PLL) has the same structure as the Kalman filter. In this paper, closed-form expressions of the corresponding Kalman gain values are derived both in acquisition and tracking modes of the PLL     

Reconfigurable phase-locked loops on FPGA utilising intrinsicsynchronisability

A new digital phase-locked loop (PLL), utilising the intrinsic synchronisability of electrical oscillators, on a field-programmable gate array has been developed. By interconnecting such PLLs, a dynamically reconfigurable clock network was formed. This has previously been difficult with conventional PLL techniques     

Design of loop filter in phase-locked loops

An exact method for designing loop filters in third-order PLLs is presented. The method is simple and results in a PLL with superior loop dynamics and improved output jitter while maintaining the same loop bandwidth compared to that of a PLL designed using the conventional approach. The method is readily applicable to higher order PLLs     

Phased array beam steering using phase-locked loops

Phase-locked loops can be used as linear voltage-controlled phase shifters for phased antenna arrays. Results are presented showing that they offer considerable flexibility, both in configuration and modes of control, in beam steering and other more complex beamforming applications.<>     

A highly stable VCO for application in monolithic phase-locked loops

The characteristics of the voltage-controlled oscillator (VCO) are generally the most important in determining the overall system performance of phase-locked loops. A new VCO is described which achieves a better combination of temperature stability, speed, and power dissipation than could previously be obtained in a monolithic integrated circuit.     

A stabilization technique for phase-locked frequency synthesizers

A stabilization technique is presented that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay cell, obviating the need for resistors in the loop filter. A 2.4-GHz CMOS frequency synthesizer employing the technique settles in approximately 60 /spl mu/s with 1-MHz channel spacing while exhibiting a sideband magnitude of -58.7 dBc. Designed for Bluetooth applications and fabricated in a 0.25-/spl mu/m digital CMOS technology, the synthesizer achieves a phase noise of -112 dBc/Hz at 1-MHz offset and consumes 20 mW from a 2.5-V supply.     

Improved Allan variance real-time processing system to measure frequency tracking error of heterodyne optical phase-locked loops

The performance of an Allan variance measuring system was drastically improved by employing time interval analysis incorporating a beat frequency method. It was used to evaluate the performance of a heterodyne optical phase-locked loop with a very low optical frequency tracking error of 0.4mHz at the integration time of 70s. Advantages of the system are precise measurement for highly stable frequency sources with good reproducibility and simple structure.<>     

Comparison between first-order digital and analogue phase-locked loops

The letter deals with a comparison between a binary quantised digital phase-locked loop and a conventional one. It is shown that, under the condition of equal acquisition times, a digital loop performs better for low signal/noise ratios.     

Digital phase-locked loops tracked by a relay sensor

An optimal algorithm is presented for tracking the phase of a slowly modulating signal by means of digital sampling of its sign. Error bounds and a numerical illustration are given     

A new technique for improving the acquisition performance of second-order phase-locked loops

In this letter a simple technique for improving the acquisition performance of all second-order phase-locked loops is described. The method overcomes many of the limitations of previous techniques and can be easily incorporated into existing systems. Preliminary results are described.     

SEC中的全数字锁相环的分析及设计

文章首先介绍了全数字锁相环(ADPLL)的基本结构和工作原理,并进行了数学建模,计算了其主要的参数指标;然后,针对SDH设备时钟(SEC)设计了一种切实可行的低抖动ADPLL的电路结构,并对其各个组成部分进行了具体的电路分析和设计,通过微机适当配置,可以使该设计的结果得到优化;最后,通过现场可编程门阵列(FPGA)验证,给出了测试结果.     

A digital phase-locked loop for generating frequency discriminating codes and frequency multiplication

A new digital phase-locked loop system realizale by a few off-the shelf digital ICs is described. The system is locked by tracking the input square wave and produces an output binary code whose value is proportional to the input frequency. It is characterized by wide locking range and fast capture time down to very low frequencies (<1 Hz) and suited to low frequency multiplication. Asymmetry in capture time, however, limits its use as an FM demodulator to only slowly varying signals.     

Phase-plane analysis of phase-locked loops with rapidly varying phase error

Nonlinear behaviour of phase-locked loops with rapidly varying phase error is examined by using computer phase-plane analysis. The phase variation is modeled by a sinusoidal function. Threshold loop parameters are presented for both sinusoidal and sawtooth phase comparators.