Millimeter-wave voltage-controlled oscillators in 0.13-/spl mu/m CMOS technology

This paper describes the design of CMOS millimeter-wave voltage controlled oscillators. Varactor, transistor, and inductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 /spl mu/m result both good quality factor (>12) and C/sub max//C/sub min/ ratio (/spl sim/3) in the 0.13-/spl mu/m CMOS process used for the study. The components were utilized to realize a VCO operating around 60 GHz with a tuning range of 5.8 GHz. A 99-GHz VCO with a tuning range of 2.5 GHz, phase noise of -102.7 dBc/Hz at 10-MHz offset and power consumption of 7-15mW from a 1.5-V supply and a 105-GHz VCO are also demonstrated. This is the CMOS circuit with the highest fundamental operating frequency. The lumped element approach can be used even for VCOs operating near 100-GHz and it results a smaller circuit area.     

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads).     

A 0.83-2.5-GHz continuously tunable quadrature VCO

A quadrature VCO with /spl plusmn/50% continuous 0.83-2.5-GHz tuning range is presented. It is based on a core LC-QVCO with /spl plusmn/20% tuning range, a single sideband mixer (SSBM), two frequency dividers and a multiplexer. The circuit has been implemented in a 0.13-/spl mu/m 1.2-V CMOS technology. The additional area with respect to the core LC-QVCO is 100 /spl mu/m/spl times/100 /spl mu/m. Quadrature error is less than 2/spl deg/; the phase noise is less than -120 dBc/Hz @ 1 MHz over the whole tuning range and is mainly due to the LC-QVCO. Spurs are more than 34 dB below the fundamental in the worst case.     

Low phase noise IP VCO for multistandard communication using a 0.35-/spl mu/m BiCMOS SiGe technology

In this letter, we report that a commonly used 0.35-/spl mu/m, 60-GHz-F/sub MAX/ BiCMOS SiGe monolithic microwave integrated circuit (MMIC) technology is able to provide very low phase noise signal generation in the X-band frequency range. This statement has been demonstrated using a differential LC voltage-controlled oscillator (VCO) in which varactors are realized with metal-oxide semiconductor (MOS) transistors and inductors with a patterned ground shield technology. This VCO features an output power signal in the range of -5 dBm and exhibits a phase noise of -96 dBc/Hz at a frequency offset of 100kHz from carrier and -120 dBc/Hz at a frequency offset of 1 MHz. The VCO features a tuning range of 430 MHz or 4.3% of its operating frequency. Its power consumption is in the range of 70 mW (200 mW with buffers circuits) for a chip size of 800/spl times/1000 /spl mu/m/sup 2/ (including RF probe pads).     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.     

Hot-carrier and soft-breakdown effects on VCO performance

This paper systematically investigates the hot-carrier- and soft-breakdown-induced performance degradation in a CMOS voltage-controlled oscillator (VCO) used in phase-locked-loop frequency synthesizers. After deriving the closed-form equations to predict phase noise and VCO gain, we relate VCO RF performance such as phase noise, tuning range, and gain of VCO subject to electrical stress. The circuit degradations predicted by analytical model equations are verified by SpectraRF simulation using parameters extracted from the experimental data of 0.16 /spl mu/m CMOS technology. BERT simulation results give VCO performance degradations versus operation time.     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

9.3-10.4-GHz-band cross-coupled complementary oscillator with low phase-noise performance

A fully integrated 10-GHz-band voltage-controlled oscillator (VCO) has been designed and fabricated using commercial 0.18-/spl mu/m CMOS technology. The complementary cross-coupled differential topology is adopted in the design. The measured phase-noise is around -89 dBc/Hz at the offset frequency of 100 kHz from the center frequency of 9.83 GHz, the output frequency tuning range of the fabricated VCO is 1.1 GHz ranging from 9.3 to 10.4 GHz, and the power consumption of the core VCO circuit is 5.8 mW. The design is the first one that adopts the complementary cross-coupled circuit structure for 10-GHz-band oscillators, and whose performances of the VCO are the best ones for 10-GHz-band oscillators, compared with the 10-GHz-band CMOS oscillators reported earlier.     

Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-/spl mu/m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm/sup 2/ and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.     

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.     

A low-phase-noise K-band CMOS VCO

A novel circuit topology for low-phase-noise voltage controlled oscillators (VCOs) is presented in this letter. By employing a PMOS cross-coupled pair with a capacitive feedback, superior circuit performance can be achieved especially at higher frequencies. Based on the proposed architecture, a prototype VCO implemented in a 0.18-/spl mu/m CMOS process is demonstrated for K-band applications. From the measurement results, the VCO exhibits a 510-MHz frequency tuning range at 20GHz. The output power and the phase noise at 1-MHz offset are -3dBm and -111dBc/Hz, respectively. The fabricated circuit consumes a dc power of 32mW from a 1.8-V supply voltage.     

A 5-GHz fully integrated full PMOS low-phase-noise LC VCO

A 5-GHz fully integrated, full PMOS, low-phase-noise and low-power differential voltage-controlled oscillator (VCO) is presented. This circuit is implemented in a 0.35-/spl mu/m four-metal BiCMOS SiGe process. At 2.7-V power supply voltage and a total power dissipation of only 13.5 mW, the proposed VCO features a worst case phase noise of -97 dBc/Hz and -117 dBc/Hz at 100 kHz and 1 MHz frequency offset, respectively. The oscillator is tuned from 5.13 to 5.68 GHz with a tuning voltage varying from 0 to 2.7 V.     

A low-power ka-band Voltage-controlled oscillator implemented in 200-GHz SiGe HBT technology

An integrated low-power low phase-noise Ka-band differential voltage-controlled oscillator (VCO) is developed in a 0.12-/spl mu/m 200-GHz silicon-germanium heterojunction bipolar transistor technology. The use of line inductors instead of transmission lines is demonstrated to be feasible in LC-tuned resonators for Ka-band applications. This VCO can operate from a supply voltage of 1.6-2.5 V. A single-sideband phase noise of -99 dBc/Hz at 1-MHz offset from the carrier frequency of 33 GHz is achieved, together with a VCO figure-of-merit of -183.7 dBc/Hz. The frequency tuning constant of the VCO in the linear regime is -0.547 GHz/V.     

Posttuning Drift of a Transferred-Electron-Device Voltage-Controlled Oscillator (Short Papers)

An experimental study was done on the parameters affecting the frequency drift of a transferred-eletron-device (TED) controlled oscillator (VCO) after tuning from one frequency to another within its tuning band. For the VCO measured, reduction in frequency drift was observed and measured when: 1) the output power was reduced voltage either by decoupling the load or by using a lower power TED; 2) the voltage swing was restricted so as to draw less than 10 mu A forward or reverse current; and 3) when a varactor with a high Q was used. With 5-mW output the TED VCO had a frequency drift less than 2.5 MHz from 1 mu s to 100 ms when step tuning the frequency anywhere in the frequency band from 6.8 to 9.1 GHz.     

A 900-MHz 1.5-V CMOS voltage-controlled oscillator using switched resonators with a wide tuning range

A 900-MHz fully integrated VCO was fabricated in a 0.18-/spl mu/m foundry CMOS process. Under 1.5 V power supply, this VCO can be tuned from 667 MHz to 1156 MHz which corresponds to a 53.6% tuning range. The VCO has nearly constant phase noise over the whole tuning frequency, credit to the switched resonators used in this VCO. The phase noise at a 600 kHz offset is -123.1 dBc/Hz at 1125 MHz center frequency and -124.2 dBc/Hz at 667 MHz center frequency.     

A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver

A PLL technique is introduced that enables fast and accurate frequency switching, independent of the loop bandwidth. It uses separate tuning paths, each driving a separate VCO tune port. Different frequencies are produced by letting the VCO make different weighted combinations of the stable tuning voltages. The PLL converges to the stable tuning voltages by switching it a few times between the desired frequencies and tuning paths. Once the stabilized tuning voltages are found, one can switch between frequencies as fast as one can switch between K/sub VCO/s. The technique is applied to a 3.5-GHz integer-N PLL to enable fast jumping of the local oscillator (LO) frequency when an 802.11 transceiver is switched between a low and a zero intermediate frequency (LIF/ZIF). It uses dual phase/frequency detectors (PFD), charge pumps (CPs), and on-chip loop filters to control two separate low-leakage VCO tune ports. Each PFD/tune port combination can be (de)activated separately, without disturbing the loop filters' charge. The 50-kHz bandwidth PLL achieves a measured 7-MHz jump with /spl plusmn/20 kHz accuracy within 6 /spl mu/s. The measured phase noise is -123 dBc/Hz at 1-MHz offset.     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration

A 1.8-GHz LC VCO designed in a 0.18-/spl mu/m CMOS process achieves a very wide tuning range of 73% and measured phase noise of -123.5 dBc/Hz at a 600-kHz offset from a 1.8-GHz carrier while drawing 3.2 mA from a 1.5-V supply. The impacts of wideband operation on start-up constraints and phase noise are discussed. Tuning range is analyzed in terms of fundamental dimensionless design parameters yielding useful design equations. An amplitude calibration technique is used to stabilize performance across the wide band of operation. This amplitude control scheme not only consumes negligible power and area without degrading the phase noise, but also proves to be instrumental in sustaining the VCO performance in the upper end of the frequency range.     

Large-signal analysis of MOS varactors in CMOS -G/sub m/ LC VCOs

MOS varactors are used extensively as tunable elements in the tank circuits of RF voltage-controlled oscillators (VCOs) based on submicrometer CMOS technologies. MOS varactor topologies include conventional D = S = B connected, inversion-mode (I-MOS), and accumulation-mode (A-MOS) structures. When incorporated into the VCO tank circuit, the large-signal swing of the VCO output oscillation modulates the varactor capacitance in time, resulting in a VCO tuning curve that deviates from the dc tuning curve of the particular varactor structure. This paper presents a detailed analysis of this large-signal effect. Simulated results are compared to measurements for an example 2.5-GHz complementary -G/sub m/ LC VCO using I-MOS varactors implemented in 0.35-/spl mu/m CMOS technology.     

Simple K-band MMIC VCO utilizing a miniaturized hairpin resonator and a three-terminal p-HEMT varactor with low phase noise and high output power properties

Presents a fully monolithic K-band MMIC voltage-controlled oscillator (VCO) implemented by using a 0.25 /spl mu/m AlGaAs/InGaAs pseudomorphic HEMT (p-HEMT) technology. The use of a half-wavelength miniaturized hairpin-shaped resonator and a three-terminal p-HEMT varactor was effective in reducing the chip size and simplifying fabrication processes of the microwave MMIC VCO without impairing the performance of the circuit. The VCO provides a typical output power of 11.5 dBm at 20.8 GHz and a free-running phase noise of -82 dBc/Hz at 100 kHz offset and -95 dBc/Hz at 1 MHz offset. It also shows a tuning range of 70 MHz with little reduction in output power and high yield properties. The chip size of the MMIC VCO is 1.5 /spl times/ 2.0 mm/sup 2/.