BiCMOS结构中阱特性的研究

叙述了以双极型工艺为主体的ＢｉＣＭＯＳ结构中ｐ阱电阻比值非线性的特性及其与芯片合格率的关系。在ｐ阱下面采用埋层，抑制或消除了ＢｉＣＯＭＳ中；ｐ阱结构的寄生效应，从而提高了芯片合格率。     

一种双扩散p阱nMOS器件新结构

本文介绍了一种适用于ＶＤＭＯＳ功率集成电路的双扩散ｐ阱ｎＭＯＳ器件新结构，该结构具有与ＶＤＭＯＳ工艺完全兼容和加工工艺简单的特点。利用这种结构可实现ｎＭＯＳ处理电路与衬底间的ｐｎ结隔离，并且隔离电压接近ＶＤＭＯＳ管的耐压。通过调节源、漏扩散窗口间距，可以在小范围内调整ｎＭＯＳ管的阈值电压。这种双扩散ｎＭＯＳ器件结构，特别适合于制作单驱动器件的ＭＯＳ功率集成电路。     

短沟道CMOS／SIMOX器件及电路的辐照特性研究

利用薄膜全耗尽ＣＭＯＳ／ＳＯＩ工艺成功地研制了沟道长度为１．０μｍ的薄膜抗辐照ＳＩＭＯＸＭＯＳＦＥＴ、ＣＭＯＳ／ＳＩＭＯＸ反相器和环振电路，Ｎ和ＰＭＯＳＦＥＴ在辐照剂量分别为３ｘ１０５ｒａｄ（Ｓｉ）和７ｘ１０５ｒａｄ（Ｓｉ）时的阈值电压漂移均小于１Ｖ，１９级ＣＭＯＳ／ＳＩＭＯＸ环振经过５ｘ１０５ｒａｄ（Ｓｉ）剂量的电离辐照后仍能正常工作，其门延迟时间由辐照前的２３７ｐｓ变为３２８ｐｓ。     

高速BiCMOS工艺研究

研究开发一种准２μｍ高速ＢｉＣＭＯＳ工艺，该工艺采用乍对准双埋双阱及外延结构。外延层厚度２．０－２．５μｍ，器件间采用多晶硅缓冲层局部氧化隔离，双极器件采用多晶硅发射极晶体管。利用此工艺试制出ＢｉＣＭＯＳ２５级环振，在负载电容ＣＬ＝０．８ｐＦ条件下，平均门延迟时间ｔｑｄ＝０．８４ｎｓ，功耗为０．３５ｍＷ／门，驱动能力 ０．６２ｎｓ／ｐＦ，明显ＣＭＯＳ门。     

双固相外延技术及高性能1μmCMOS／SOS器件的研究

本文较为详细地介绍了能有效地改善ＳＯＳ材料结晶质量的双固相外延ＤＳＰＥ工艺，给出了优化的工艺条件．通过比较用ＤＳＰＥ及普通ＳＯＳ材料制作的ＣＭＯＳ／ＳＯＳ器件和电路的特性可以看出，采用ＤＳＰＥ工艺能显著改善ＳＯＳ材料的表面结晶质量，应用ＤＳＰＥ工艺在硅层厚度为３５０ｎｍ的ＳＯＳ材料上成功地研制出了沟道长度为１μｍ的高性能ＣＭＯＳ／ＳＯＳ器件和电路，其巾ＮＭＯＳＦＥＴ及ＰＭＯＳＦＥＴ的泄漏电流分别为２．５ｐＡ和１．５ｐＡ，１９级ＣＭＯＳ／ＳＯＳ环形振荡器的单级门延迟时间为３２０ｐｓ．     

双多晶硅栅SOI MOS器件的研究

采用多晶硅栅全耗尽ＣＭＯＳ／ＳＩＭＯＸ工艺成功研制出多晶硅栅器件,其中Ｎ＋栅ＮＭＯＳ管的阈值电压为０．４５Ｖ,Ｐ＋栅ＰＭＯＳ管的阈值电压为－０．２２Ｖ,在１Ｖ和５Ｖ电源电压下多晶硅栅环振电路的单级门延迟时间分别为１．７ｎｓ和３５０ｐｓ,双多晶硅栅ＳＯＩ技术将是低压集成电路的一种较好选择。     

1.5μm双层布线Ｎ阱CMOS工艺研究

给出了１．５μｍ双层布线Ｎ阱ＣＭＯＳ工敢研究流程，叙述了研究中一些关键技术。     

S1240专用DSPLSI

本文描述了采用等比例缩小基本规则和Ｎ阱ＨＣＭＯＳ双层Ｐｏｌｙ技术，制造出Ｓ１２４０数字程控电话交换机专用的数字值号处理器（ＤＳＰ）。电路典型工作频率为４ＭＨＺ，功耗〈７５ｍＷ，达到了国外同类产品性能指标。     

高速BiCMOS工艺研究

研究开发了一种准２μｍ高速ＢｉＣＭＯＳ工艺，采用自对准双埋双阱及外延结构．外延层厚度为２．０～２．５μｍ，器件间采用多晶硅缓冲层局部氧化（简称ＰＢＬＯＣＯＳ）隔离，双极器件采用多晶硅发射极（简称ＰＳＥ）晶体管．利用此工艺已试制出ＢｉＣＭＯＳ２５级环振电路，在负载电容ＣＬ＝０．８ｐＦ条件下，平均门延迟时间ｔｐｄ＝０．８４ｎｓ，功耗为０．３５ｍＷ／门，驱动能力为０．６２ｎｓ／ｐＦ．明显优于ＣＭＯＳ门．     

局部网络中的TOKEN—PASSING技术

本文通过对ＴＯＫＥＮ－ＰＡＳＳＩＮＧ协议与ＣＳＭＡ协议的比较，说明ＴＯＫＥＮ－ＰＡＳＳＩＮＧ技术克服了ＣＳＭＡ协议的不足，从实例中阐述了该技术在局部网络中的重要地位及其优点。     

A high-density MOS static RAM cell using the lambda bipolar transistor

Based upon the common-collector lambda bipolar transistor (LBT), which is built with p-well NMOS, and the parasitic n-p-n BJT in a CMOS IC, a novel MOS static RAM cell called the LBT cell is proposed. In this new cell, the LBT and two poly-Si resistors form a bistable element with a PMOS access transistor. With the minimum feature size F, the optimal cell area of 32 F/SUP 2/ can be realized by using the silicide contact and small p-well spacing. The READ-WRITE operation is simulated. Due to the need of precharging before reading and the rather slow recovery after reading, suitable peripheral circuits should be designed.     

130 nm NMOS器件的单粒子辐射电荷共享效应

研究了同一p阱内两个130nm NMOS器件在受到重离子辐射后产生的电荷共享效应。使用TCAD仿真构造并校准了130nm NMOS管。研究了在有无p+保护环结构及不同器件间距下,处于截止态的NMOS晶体管之间的电荷共享,给出了电荷共享效应与SET脉冲电流产生的机理。同时分析了NMOS晶体管中的寄生双极管效应对反偏漏体结电荷收集的加剧作用。仿真结果表明,p+保护环可以有效地减小NMOS器件间的电荷共享,加速SET脉冲电流的泄放,证实了p+保护环对器件抗单粒子辐射的有效性,从而给出了该方法在抗单粒子辐射器件版图设计中的可行性。     

Digital CMOS IC's in 6H-SiC operating on a 5-V power supply

A CMOS technology in 6H-SiC utilizing an implanted p-well process is developed. The p-wells are fabricated by implanting boron ions into an n-type epilayer. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells using a thermally grown gate oxide. The resulting NMOS devices have a threshold voltage of 3.3 V while the PMOS devices have a threshold voltage of -4.2 V at room temperature. The effective channel mobility is around 20 cm ²/Vs for the NMOS devices and around 7.5 cm²/Vs for the PMOS devices. Several digital circuits, such as inverters, NAND's, NOR's, and 11-stage ring oscillators are fabricated using these devices and exhibited stable operation at temperatures ranging from room temperature to 300°C. These digital circuits are the first CMOS circuits in 6H-SiC to operate with a 5-V power supply for temperatures ranging from room temperature up to 300°C     

Improving the yield and reliability of the bulk-silicon HV-CMOS by adding a P-well

In this paper, a novel high-yield and high-reliability High Voltage CMOS (HV-CMOS) compatible with 0.6 μm rules standard Bulk-Silicon (BS) CMOS process was proposed. The detailed discussion on how to avoid the influence of the lithography misalignment of the High Voltage PMOS (HV-PMOS) was given. The detailed analysis on the validity of the added p-well to prevent the High Voltage Double-Diffusion NMOS (HV-DNMOS) from punching through was also suggested. The experimental results show the yields of the HV-PMOS and the HV-CMOS are more than 98% and 95%, respectively, which are due to adding the p-well to HV-PMOS for eliminating the influence of the lithography misalignment during etching the unwanted thick gate oxide film of the HV-PMOS and that to HV-DNMOS for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be well applied in high voltage driver ICs, etc.     

Analysis of mesastable operation in RS CMOS flip-flops

An analysis of metastable operation in CMOS RS flip-flops is presented. An analytical formula for the flip-flop resolving time constant was derived using Shichman-Hodges model for NMOS and PMOS transistors. This formula, as related to the transistor dimensions, fabrication process parameters, and parasitic capacitance, uses proper transistor sizing to attain minimum flip-flop failure rate due to metastable operation. CMOS n-well, p-well, and twin-well flip-flop performance predicted analytically is also approved by SPICE level one simulation of transistor models. Real-time oscilloscope displays of metastable operation for two different CMOS RS flip-flop circuits are demonstrated.     

An enhanced slew rate source follower

A unity-gain buffer capable of high slew rates in both the positive and negative directions is presented. By sensing the drain current of the common-drain device in an NMOS source follower, the extent of slewing is detected, and the tail current of the source follower is dynamically adjusted. A buffer incorporating this strategy was implemented in a 2 μm p-well process. This buffer has over 4 times the negative-going slew rate and twice the bandwidth of a source follower, while requiring only 13% more static power. Moreover, the output voltage swing range is as large as that of a source follower. With a 20 pF output load, the measured 3-dB bandwidth was 9 MHz. The signal-to-total-harmonic-distortion ratio with 2 V_p-p sinewave input at a frequency of 2 MHz was better than 50 dB     

Influence of defects in gate-oxide peripheral regions on the electrical characteristics of MOS structures

Radiation-induced defect formation is studied experimentally in the gate-insulator layer and at the semiconductor-insulator interface of NMOS and PMOS structures differing in perimeter-to-area ratio. The structures are fabricated by CMOS technology on the same n-Si wafer, the NMOS structures being formed in a p-well. Heavily phosphorus doped polysilicon and noncrystalline silicon dioxide are used as the gate and insulator materials, respectively. The devices considered are MOS varactors, MOS diodes, and MOSFETs. Capacitance-voltage characteristics are measured on the MOS varactors and diodes. The gate-voltage dependence is examined of surface conduction for the MOSFETs and the surface-recombination emitter-current component for the MOS diodes. The results are used to characterize defect formation in peripheral gate-oxide regions and the lightly doped part of the source (emitter) and the drain, as well as in the central gate-oxide region and at the Si/SiO₂ interface. The peripheral oxide regions are found to have a two-sided influence on the performance of the MOS structures. On the one hand, they act as a drain of uncombined hydrogen from the gate oxide, so that the effectiveness of defect deactivation by hydrogen depends on the perimeter-to-area ratio. On the other hand, the peripheral regions, particularly their corners, may have an elevated density of latent process-induced defects that can be activated by radiation, voltage, or thermal stress.     

Boron channel-stop design for poly-buffered LOCOS using selectiveboron segregation

A boron channel-stop compensation technique using a selective polysilicon etch prior to field oxidation is proposed for CMOS isolation technologies which use polysilicon buffered LOCOS. The stress relief polysilicon layer is selectively removed over the n-well field regions which results in additional boron segregation into the growing field oxide while the polysilicon layer is being oxidized over the p-well field regions. The resulting field threshold voltages are increased by as much as 11.6 and 6.4 V for the p-well and n-well MOS capacitors, respectively     

A retrograde p-well for higher density CMOS

A new technique for CMOS p-well (or n-well) formation is described, making use of a deep implant followed by a brief anneal. This results in a retrograde profile, permitting a much shallower well, a large reduction in p-n channel device spacing (5-6 µm versus 10-15 µm), and an opportunity to reduce the risk of latch-up. This technique is more conducive to scaling-with the promise of significantly better performance-than conventional well formation methods. The retrograde p-well has been successfully applied to a linearly shrunk bulk CMOS 4K static RAM, demonstrating its feasibility.     

Alpha-particle-induced charge transfer between n+regions in high-density trench DRAM with isolated p-well structures

Alpha-particle-induced charge transfer (ACT) between n⁺ regions inherent in isolated p-well structures is described. The isolated p-well structures in Si ICs such as advanced trench DRAM cells can cause anomalous charge collection through the ACT. The collected charge is evaluated for advanced trench DRAM cells by circuit and device simulations. In addition, this mechanism is compared to charge transfer in devices with ordinary p-well structures by means of simulations of generalized model structures. It is concluded that ACT with isolated p-well structures may cause a significant problem with scaling, whereas ACT with ordinary p-well structures can be avoided by following a proposed scaling law