一种应用于不可分层LDPC码的并行分层译码算法

该文针对不可分层LDPC码无法利用分层算法进行译码的问题,提出了一种并行分层置信度传播(Parallel-Layered Belief-Propagation,PLBP)译码算法。与传统分层算法不同,该算法在译码时并行进行各层更新,串行进行层内各行更新。这种译码机制使得同一变量节点在各层内不同时进行更新,从而实现各变量节点在一次迭代中分层递进更新的算法目标。仿真表明,在不增加译码复杂度的情况下,该文提出的PLBP算法与传统的洪水算法相比,误码性能更优,而且所需要的平均迭代次数降低了约50%。此外,PLBP算法采用了合并的节点更新运算,最终使该算法达到的译码速度约为洪水算法的4倍。     

快速收敛的EG-LDPC译码算法设计实现

欧式几何构造的LDPC码属于不可分层的LDPC码,无法采用TDMP算法译码结构,针对该问题设计实现了一种新型分层译码器。在Xilinx V5 FPGA上实现了码长为1023、码率为0.781 EG-LDPC 码的译码器设计。仿真验证表明：理论上该方法与优化的规范化最小和译码算法相比,迭代次数减少一倍,存储资源消耗得到降低,而误码性能几乎相同。FPGA实现上,译码输出与MATLAB定点仿真给出的结果相同,误码性能由于量化和限幅处理与理论值相比约有0.3dB的损失。在时钟频率为50MHz串行处理各分层时,吞吐量为49.7Mbps。     

多元LDPC码分层译码算法及其在QPSK调制下的应用

文章将二元LDPC码对数域的分层译码算法成功运用在多元LDPC码的译码过程当中。仿真结果表明,在理想加性高斯白噪声信道环境下,QPSK调制时,多元LDPC码分层译码算法的性能明显优于传统的对数域译码算法,因此它可以有效提升消息传递算法的收敛速度,减少译码延时。     

多元LDPC码列分层DBC译码算法

针对多元LDPC码扩展最小和（Extended Min Sum,EMS）译码算法收敛速度慢、运算复杂度高的问题,提出一种多元LDPC码列分层动态检泡（Dynamic Bubble-Check,DBC）译码算法。首先对变量节点按不同列重进行分层处理,译码时率先更新列重较大分层的变量节点消息,不同层之间采用串行方式进行消息传递,通过并串结合的方式降低译码迭代次数。在校验节点消息更新过程中,采用动态检泡方法减少EMS算法中的运算量,降低算法复杂度。仿真结果表明,在几乎不损失性能的前提下,该算法的平均最大迭代次数仅为EMS译码算法的50%,复杂度降低为EMS算法的50%。     

基于FMS算法的多元LDPC码的译码器设计

多元LDPC码具有比二元LDPC码更好的应用前景,但是过高的译码复杂度限制了它在实际系统的中的应用.在扩展最小和(EMS)系列的译码算法中,固定路径最小和(FMS)译码算法不仅具有很低的复杂度,还具有良好的性能.针对如何实现低复杂度的多元LDPC译码器,对FMS算法和分层译码算法进行了介绍,对FMS算法和EMS算法的性...     

多码率LDPC码高速译码器的设计与实现

低密度奇偶校验码(LDPC码)以其接近香浓极限的性能得到了广泛的应用.如何在.FPGA上实现多码率LDPC码的高速译码,则是LDPC码应用的一个焦点.本文介绍了一种多码率LDPC码及其简化的和积译码算法;设计了这种多码率LDPC码的高速译码器,该译码器拥有半并行的运算结构和不同码率码共用相同的存储单元的存储资源利用结构,并以和算法与积算法功能单元同时工作的机制交替完成对两个码字的译码,提高了资源利用率和译码速率.最后,本文采用该结构在FPGA平台上实现了码长8064比特码率7/8、6/8、5/8、4/8、3/8五个码率的多码率LDPC码译码器.测试结果表明,译码器的有效符号速率达到200Mbps.     

动态自适应低密度奇偶校验码译码器的FPGA实现

在复杂深空通信环境中,自适应能力的强弱对低密度奇偶校验(LDPC)码译码器能否保持长期稳定工作具有重要影响。该文通过对DVB-S2标准LDPC码译码器各功能模块的IP化设计,将动态自适应理论参数化映射到各功能模块中,实现动态自适应LDPC码译码器的设计。基于Stratix IV系列FPGA的验证结果表明,动态自适应LDPC译码器可以满足不同码率码长及不同性能需求下的译码。同时,单译码通道可以保证译码数据信息吞吐率达到40.9~71.7 Mbps。     

一种基于QC-LDPC码的低复杂度分层迭代译码器

针对具有准循环结构的LDPC码,设计了一种低复杂度译码器。利用校验矩阵的循环特性以及分层迭代的译码算法,对一般的分层迭代架构进行改进,实现了译码器流水线处理,有效的减少迭代时间,提高吞吐量,最后针对码长为1200的LDPC码,基于FPGA平台Kintex7 xc7k325的芯片实现了该架构设计,结果表明,该译码器只消耗了100多个Slices和几块RAM,有效节省了硬件资源,同时译码时间比一般的分层架构减少了2/3左右,吞吐量提高了约2倍,研究成果具有重要的实用价值,可应用于资源有限的低速通信领域。     

一种基于ASIP结构的LDPC译码器芯片设计

针对IEEE 802.11n标准中LDPC码多码率、多码长的特点,提出了一种基于ASIP架构的LDPC译码器设计方案。该译码器采用优化的分层译码算法、11级流水线技术以及基于ASIP结构的微指令技术,实现了4种不同码率、3种不同码长的LDPC译码功能。采用TSMC 0.18 μm CMOS工艺进行物理实现,该译码器芯片面积为3.65 mm²。测试结果表明,该设计满足IEEE 802.11n标准的译码要求。     

多元LDPC码串行译码算法在光纤通信中的应用

将串行BP译码算法用在多元LDPC码中,降低了在光纤传输系统中的译码延时.详细介绍了在多元LDPC码中的串行BP译码算法和光纤通信系统的仿真模型.给出了在采用串行BP算法的LDPC译码器中,译码最大迭代数量对译码性能的影响,比较了采用传统的BP算法扣串行BP算法时LDPC译码器的性能.结果表明,采用串行BP算法确实能够提升LDPC译码器的收敛速度.     

基于FPGA的大围数QC_LDPC码的译码器

针对QC_LDPC码的短环对码性能的重要影响,采用了1种围数为8的QC_LDPC码设计。算法首先分别对3个不同的子矩阵进行移位运算,每个子矩阵分别与它们移位后生成的子矩阵共同组合形成1个新的子矩阵,然后再将新生成的3个子矩阵组合成1个矩阵构成基阵,最后将该矩阵转置后用单位矩阵及其移位矩阵随机扩展即可得到所需校验矩阵。根据该校验矩阵的特殊结构,采用分层迭代译码算法,选用Altera公司的Stratix III系列FPGA,实现码率为1/2、码长为3456的正规(3,6)QC_LDPC码译码器的布局布线。     

Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding

Reed-Solomon (RS) codes are one of the most widely utilized block error-correcting codes in modern communication and computer systems. Compared to hard-decision decoding, soft-decision decoding offers considerably higher error-correcting capability. The Koetter-Vardy (KV) soft-decision decoding algorithm can achieve substantial coding gain, while maintaining a complexity polynomial with respect to the code word length. In the KV algorithm, the interpolation step dominates the decoding complexity. A reduced complexity interpolation architecture is proposed in this paper by eliminating the polynomial updating corresponding to zero discrepancy coefficients in this step. Using this architecture, an area reduction of 27% can be achieved over prior efforts for the interpolation step of a typical (255, 239) RS code, while the interpolation latency remains the same     

Low Complexity Decoder Architecture for Low-Density Parity-Check Codes

In this paper, we propose a low complexity decoder architecture for low-density parity-check (LDPC) codes using a variable quantization scheme as well as an efficient highly-parallel decoding scheme. In the sum-product algorithm for decoding LDPC codes, the finite precision implementations have an important tradeoff between decoding performance and hardware complexity caused by two dominant area-consuming factors: one is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of the nonlinear function Ψ(x). The proposed variable quantization schemes offer a large reduction in the hardware complexities for LUT and memory. Also, an efficient highly-parallel decoder architecture for quasi-cyclic (QC) LDPC codes can be implemented with the reduced hardware complexity by using the partially block overlapped decoding scheme and the minimized power consumption by reducing the total number of memory accesses for updated messages. For (3, 6) QC LDPC codes, our proposed schemes in implementing the highly-parallel decoder architecture offer a great reduction of implementation area by 33% for memory area and approximately by 28% for the check node unit and variable node unit computation units without significant performance degradation. Also, the memory accesses are reduced by 20%.     

基于串行消息传递机制的QC-LDPC码快速译码算法研究

针对准循环LDPC(QC-LDPC)码基于洪水消息传递机制译码算法的不足,该文提出了一种快速的分组串行译码算法。该算法通过将LDPC码的校验节点(或变量节点)按一定规则划分成若干个子集,在每一轮迭代过程中,依次对各个子集中的校验节点(或变量节点)并行地进行消息更新,提高了译码速度。同时根据分组规则,提出了一种有效的分组方法,并通过分析发现基于循环置换阵的准循环LDPC码非常适合采用这种分组译码算法进行译码。通过对不同消息传递机制下准循环LDPC码译码算法性能的仿真比较,验证了在复杂度不增加的情况下,该译码算法在继承了串行译码算法性能优异和迭代收敛快等优点的同时,极大地提高了准循环LDPC码的译码速度。分析表明,分组串行译码算法译码速度至少为串行译码算法的p倍(p为准循环LDPC码校验矩阵中循环置换阵的行数或列数)。     

Further Exploring the Strength of Prediction in the Factorization of Soft-Decision Reed–Solomon Decoding

Reed-Solomon (RS) codes are among the most widely utilized error-correcting codes in digital communication and storage systems. Among the decoding algorithms of RS codes, the recently developed Koetter-Vardy (KV) soft-decision decoding algorithm can achieve substantial coding gain, while has a polynomial complexity. One of the major steps of the KV algorithm is the factorization. Each iteration of the factorization mainly consists of root computations over finite fields and polynomial updating. To speed up the factorization step, a fast factorization architecture has been proposed to circumvent the exhaustive-search-based root computation from the second iteration level by using a root-order prediction scheme. Based on this scheme, a partial parallel factorization architecture was proposed to combine the polynomial updating in adjacent iteration levels. However, in both of these architectures, the root computation in the first iteration level is still carried out by exhaustive search, which accounts for a significant part of the overall factorization latency. In this paper, a novel iterative prediction scheme is proposed for the root computation in the first iteration level. The proposed scheme can substantially reduce the latency of the factorization, while only incurs negligible area overhead. Applying this scheme to a (255, 239) RS code, speedups of 36% and 46% can be achieved over the fast factorization and partial parallel factorization architectures, respectively.     

Efficient VLSI Architecture for Soft-Decision Decoding of Reed–Solomon Codes

Reed–Solomon (RS) codes have very broad applications in digital communication and storage systems. The recently developed algebraic soft-decision decoding (ASD) algorithms of RS codes can achieve substantial coding gain with polynomial complexity. Among the ASD algorithms with practical multiplicity assignment schemes, the bit-level generalized minimum distance (BGMD) decoding algorithm can achieve similar or higher coding gain with lower complexity. ASD algorithms consist of two major steps: the interpolation and the factorization. In this paper, novel architectures for both steps are proposed for the BGMD decoder. The interpolation architecture is based on the newly proposed Lee-O'Sullivan (LO) algorithm. By exploiting the characteristics of the LO algorithm and the multiplicity assignment scheme in the BGMD decoder, the proposed interpolation architecture for a (255, 239) RS code can achieve 25% higher efficiency in terms of speed/area ratio than prior efforts. Root computation over finite fields and polynomial updating are the two main steps of the factorization. A low-latency and prediction-free scheme is introduced in this paper for the root computation in the BGMD decoder. In addition, novel coefficient storage schemes and parallel processing architectures are developed to reduce the latency of the polynomial updating. The proposed factorization architecture is 126% more efficient than the previous direct root computation factorization architecture.      

Design and analysis of three-dimensional OCDMA code families

A new code design algorithm for application in three-dimensional (3D) optical code division multiple access (OCDMA) for asynchronous optical fiber communication is proposed. 3D refers to space-wavelength-time codes. The performance analysis of the proposed algorithm in 3D multiple pulses per plane (MPP) codes is shown. This design ensures a maximum cross-correlation of ‘1’ between any two codes. The performance metrics that have been investigated are the bit error rate due to multiple access interference (MAI) for different values of the number of simultaneous users and, cardinality for different values of temporal length.     

On 2-D recursive LMS algorithms using ARMA prediction for ADPCMencoding of images

A two-dimensional (2D) linear predictor which has an autoregressive moving average (ARMA) representation well as a bias term is adapted for adaptive differential pulse code modulation (ADPCM) encoding of nonnegative images. The predictor coefficients are updated by using a 2D recursive LMS (TRLMS) algorithm. A constraint on optimum values for the convergence factors and an updating algorithm based on the constraint are developed. The coefficient updating algorithm can be modified with a stability control factor. This realization can operate in real time and in the spatial domain. A comparison of three different types of predictors is made for real images. ARMA predictors show improved performance relative to an AR algorithm.     

基于联合判决消息传递机制的LDPC码译码算法研究

采用消息传递算法(Message passing algorithm)对LDPC码进行译码时,变量消息的振荡会引起错误的发生.本文以(600.300)非规则LDPC码仿真实验为例分析了不同译码效果下判决消息均值的分布特点,并结合环的特点,分析了译码产生错误判决的原因.研究了"纠删"型消息传递机制和联合判决迭代停止准则,针对判决消息出现振荡情况,提出以"纠删"方式处理变量消息的更新,并结合变量节点判决消息均值分布趋势与伴随式结果确定迭代终止条件.在此基础上,提出一种新的LDPC码译码算法.仿真分析表明,新的译码算法能够在减少迭代次数和降低译码复杂度的同时,有效提高译码的纠错性能.