数字下变频中的FPGA高效滤波器设计

介绍了一种在FPGA上实现高效窄带有限冲击响应滤波器(FIR)的设计方法.该方法利用数字下变频抗混叠滤波器的多速率和窄带的特点,采用插值FIR滤波器(IFIR)和多相滤波器相结合的设计思路,实现了该滤波器的高效设计.     

一种基于TMS320C5402的数字IIR滤波器设计

数字IIR滤波器广泛地应用于数字信号处理领域。本文主要介绍了如何在定点DSP芯片上实现IIR数字滤波器，并且通过对IIR滤波器结构的分析，对IIR数字滤波器作了一定简化，使得在定点DSP芯片上容易实现。本文采用TI公司的C54系列DSK并结合MATLAB进行仿真，达到了预期的效果。     

数字滤波器的Matlab设计与应用

数字滤波在数字信号处理中占有极其重要的地位,并且被广泛应用。研究了在Matlab环境下FIR数字滤波器的设计方法以及FIR滤波器在信号去噪方面的应用。Matlab因其强大的数据处理功能被广泛应用于工程计算,其丰富的工具箱为工程计算提供了便利,利用Matlab信号处理工具箱可以快速有效地设计各种数字滤波器,设计简单方便。     

A polymorphous computing fabric

We propose a polymorphous computing fabric-based system (FBS) well suited to digital signal processing (DSP) and image processing applications. We have implemented our design on a system on a programmable chip (SoPC). The fabric's highly parameterized cellular architecture enables customized synthesis of fabric instances to achieve high performance for different classes of applications. The system's innovative global memory provides a host control processor with random access to all the variables and instructions on the fabric. The fabric supports several computing models including multiple instruction, multiple data (MIMD); single program, multiple data (SPMD); and systolic flow and permits dynamic reconfiguration of communication patterns. To illustrate the capabilities of our approach, we present two fabric instances with implementations of representative applications including a k-means clustering algorithm, a bank of finite impulse response (FIR) filters, an N-tap FIR filter (N is the number of taps of the filter), and a vector-by-matrix multiplication. Each fabric instance holds 52 cells on the Altera Excalibur ARM embedded processor system     

一种改进型整数倍多相滤波器在FPGA中的应用

在现代通信系统中,到处都有数字信号处理（DSP）的应用。DSP设计人员的主要工具之一是有限脉冲响应（FIR）滤波器。为提高系统性能要求,所需要的FIR滤波器系数越多（有大量的抽头）,当然滤波器的响应也越好。由于大量的抽头增加了对逻辑资源的需求、增加了计算的复杂性,增加了功耗。在多速率信号处理系统中,特别是高倍数的抽取和...     

Laguerre滤波器在抗噪语音识别特征提取中的应用

为克服FIR滤波器存在的通阻带特性差、滤波器阶次高等缺点给语音识别系统带来的不利影响,采用Laguerre滤波器组代替过零峰值幅度特征提取中使用的FIR滤波器组进行前端处理。在仔细研究FIR滤波器参数确定方法的基础上,叙述了Laguerre滤波器原理及参数计算方法,并给出了计算结果。孤立词、非特定人语音识别实验结果表明,使用Laguerre滤波器不仅使识别系统抗噪性能优于使用FIR滤波器,而且滤波器阶数也大为下降。     

Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier

FIR filter plays a major role in digital image processing applications. The power and delay performance of any FIR filter depends on the switching activities between the filter coefficients (FCs) and its basic arithmetic operations (i.e., multiplication and addition) performed in the convolution equations. In this paper, a new FIR filter is designed using Enhanced Squirrel Search Algorithm (ESSA) and Variable latency Carry skip adder (VL-CSKA) based booth multiplier. The proposed ESSA algorithm selects an optimal FC by minimizing the switching activities of FC based on the ripple contents, power and Transition width parameter to meet the required specifications of FIR filter in the frequency domain. Also, the VL-CSKA based booth multiplier is proposed to reduce the delay of FIR filter with parallel addition of partial products (PPs). In this design, the VL-CSKA adders utilize variable size and compound gate-based skip logic to deduce the delay with low power. The proposed FIR filter is simulated in Xilinx working platform by developing Verilog coding. The simulation result shows that the proposed FIR filter outperforms the state-of-the-art FIR filters by consuming only 0.142 mW power with delay of 28.175 ns.     

基于高速采样的实时DDC架构技术

近年来,随着混合域示波器技术的发展,示波器既要实现传统示波器的功能,又要实现频域、调制域功能,这样在数字域信号处理中需要实现实时数字下变频（DDC）功能,实时DDC技术是实现示波器向频域和调制域功能扩展的基础,可以实现示波器的增值应用,大大扩大示波器的应用领域。本文根据高速信号采样的特点,给出了实时DDC技术架构,该架构由数字正交混频、FIR1-FIR3滤波器、HB1-HB10滤波器组成,对于20GSa/s采样数据流而言,最高支持1.25GSa/s I/Q数据流输出,最低305 kSa/s I/Q数据流输出,可满足绝大多数应用场景。对数字正交混频、FIR1滤波器、FIR2滤波器、FIR3滤波器、HB滤波器进行详细设计分析,给出了实现架构,对于FIR和HB滤波器,还给出了最佳滤波器阶数及其幅频响应曲线。对于数字正交混频、FIR1-FIR3滤波器,由于其数字速率超过了FPGA正常工作时钟范围,通过多路并行处理的手段实现信号处理。最后使用矢量信号分析软件对DDC的13种I/Q速率下的EVM性能进行了评估,分别评估了载波频率1.5GHz和3GHz的EVM性能,通过评估,EVM值大部分集中在0.5%以下,可满足使用需求。     

基于MA型分布式算法的高阶FIR滤波器设计及其FPGA实现

针对利用现有分布式算法在FPGA上实现高阶FIR滤波器时,存在资源消耗量过大和运行速度慢等问题,提出一种新型高阶FIR滤波器的FPGA实现方法。首先综合采用多相分解结构、流水线等技术对高阶FIR滤波器进行降阶处理,然后采用提出的基于二输入开关和加法器对的分布式算法结构(MA型DA结构)实现降阶后的FIR滤波器。利用ISE10.1在Xilinx Xc2vp30 7ff896 FPGA开发板上实现了一系列8阶到256阶的串行和并行结构FIR滤波器。实验结果表明,该方法有效地减少了系统的资源消耗,提高了系统的时序性能。     

Unbiased FIR Filtering with Incomplete Measurement Information

This paper proposes an unbiased filter with finite impulse response (FIR) structure for linear discrete time systems in state space form with incomplete measurement information. The measurements are transmitted from the plant to the FIR filter imperfectly due to random packet loss or sensor faults. The Bernoulli random process is used to describe the missing measurement details, and the missing data is replaced with recently transmitted data on the missing horizon. The missing horizon can hold the assumption for finite measurement of the FIR filter. Two examples are provided to demonstrate the proposed unbiased FIR (UFIR) filter robustness against temporary model uncertainty and consecutive missing measurement data compared with existing filters considering missing measurement.     

Laguerre discrete-time filter design

The design of discrete-time ideal filters by finite impulse response (FIR) method requires long FIR filter structures.This is due to the infinite impulse response characteristics of the ideal filters. Optimum Laguerre filter structures with smaller length can be used instead of FIR filters to reduce the order of the filters.In this paper the method of designing optimum Laguerre ideal low-pass, band-pass, high-pass, and band-reject filters is introduced. The optimization is performed by evaluating the Laguerre parameter and coefficients when the mean-square-error between the frequency response of the desired filter and its corresponding Laguerre network frequency response is minimum. The problem with the Laguerre filter design is the complexity of computations for evaluating the optimum Laguerre parameter. This complexity is reduced to one half by introducing a lemma.Both, analytical and numerical solutions are presented and the results are illustrated via some examples. The corresponding results yield a reduced filter order, and appropriate linear phase, with lower ripples in stop-band and pass-band compared to the conventional FIR filters.     

An alternative FIR filter for state estimation in discrete-time systems

To overcome the resulting problems of existing finite impulse response (FIR) structure filters, this paper proposes an alternative FIR filter for state estimation in discrete-time systems, which is derived from the well-known Kalman filter with recursive infinite impulse response (IIR) structure. The proposed FIR filter obtains a posteriori knowledge about the window initial condition from the most recent finite observations, while existing FIR filters handle this task arbitrarily or heuristically. The gain matrix for the proposed FIR filter incorporates a posteriori knowledge about the window initial condition during its design and is shown to be time-invariant. The proposed FIR filter is shown to have good inherent properties such as unbiasedness and deadbeat. Through extensive computer simulations, the proposed FIR filter can be shown to be comparable with the Kalman filter for the nominal system and better than that for the temporarily uncertain system.     

基于SYSGEN的AS型FIR滤波器设计

本文以FPGA为硬件核心设计数字滤波系统,提出一种低成本高效FIR滤波器的设计方法。首先利用提出的AS型FIR滤波器实现结构,降低系统逻辑资源消耗、提高系统资源利用率及系统运行速度,然后综合采用SYSGEN和ISE实现滤波器的模块化和自动化设计,简化设计过程,降低实现难度。具体在XC3S500E4f320 FPGA上实现了一系列4阶到32阶的FIR滤波器,实验结果验证了方法的有效性。     

Cascaded warped-FIR and FIR filter structure for loudspeaker equalization with low computational cost requirements

This paper proposes an improved filter structure and methodology for the equalization of loudspeakers and other audio systems. It employs a cascaded structure of a finite impulse response (FIR) filter and a warped-FIR filter in order to obtain the best performance of both types of filters. In the task of loudspeaker equalization, FIR filters achieve excellent resolution and equalization at high frequencies, but at low frequencies the resolution obtained is too poor when evaluated in a logarithmic frequency axis, that could only be improved using high order filters. To solve this lack of resolution at low frequencies, warped-FIR filters have been employed, but at the expense of decreasing the resolution of the filter at high frequencies and increasing the complexity of the filter structure and its computational cost. The proposed combination of both types of filters, combined with the correct selection of their orders, and the λ value for the warped-FIR filter, allows the FIR filter to maintain its good resolution at high frequencies and achieve enough resolution at low frequencies with the warped-FIR filter. In this way, lower order filters with lower computational cost could be obtained than when using FIR or warped-FIR only. This approximation attains a more uniform resolution of the filter when evaluated in octaves, behaving much more like human hearing, than the linear frequency resolution obtained when employing only FIR filters.     

信号FIR数字滤波后相位延迟的消除

针对信号处理中采用FIR数字滤波器对信号进行滤波后将产生相位延迟的现象,从FIR数字滤波器的相位特性出发,分析并推导了产生这种延迟现象的原因,得到了FIR数字滤波器的阶数和相位延迟的关系。采用基于波形匹配的数据扩展的方法对原始的信号进行端点延拓,再对延拓后的信号进行FIR滤波,可以很好地消除这种相位延迟的现象。Matlab仿真结果证明运用该方法滤波后的信号相位与原始信号相位一致,相位延迟被消除了。通过对信号的Simulink仿真实验及分析,也证实该方法可以有效消除FIR数字滤波器产生的相位延迟。     

改进的粒子群优化算法设计FIR低通数字滤波器

粒子群优化算法(PSO)因具有参数少、易于实现等优点,在解决优化问题时表现出很好的性能。有限长单位脉冲响应(FIR)数字滤波器因具有稳定的结构、易于实现等优点,在实际中有着很广泛的应用。因此,将基于三角函数因子的改进PSO算法(TFPSO)用于对FIR低通数字滤波器性能的优化,并将其与基于折射原理反向学习(refrPSO)、基于反向学习(OPSO)的PSO算法所设计的FIR低通数字滤波器的性能进行比较。在实验中构造出一种性能较好的适应值函数,以验证这几种改进的PSO算法所设计的FIR低通数字滤波器的性能。实验结果表明,基于三角函数因子的PSO算法滤波性能较差,而基于折射原理反向学习的PSO算法性能最佳。     

Closed-form unbiased frequency estimation of a noisy sinusoid using notch filters

In this note, the problem of the frequency estimation of a sinusoid embedded in white noise is considered. The approach used herein is the minimization of the sample variance of the output of constrained notch filters fed by the noisy sinusoid. In particular, this note focuses on closed-form expressions of the frequency estimate, which can be obtained using notch filters having an all-zeros finite-impulse response (FIR) structure. The results presented in this note are as follows: 1) it is shown that the FIR notch filters obtained from standard second-order infinite-impulse response (IIR) filters are inadequate; 2) a new second-order IIR notch filter is proposed, which provides an unbiased estimate of the frequency; 3) the FIR filter obtained from the new IIR filter provides a closed-form unbiased frequency estimate; and 4) the closed-form frequency estimate obtained using the new FIR notch filter asymptotically converges toward the Pisarenko harmonic decomposition estimator and the Yule-Walker estimator.     

基于分布式算法的高阶FIR滤波器及其FPGA实现

提出一种新的高阶FIR滤波器的FPGA实现方法。该方法运用多相分解结构对高阶FIR滤波器进行降阶处理,采用改进的分布式算法来实现降阶后的FIR滤波器。设计了一系列阶数从8到1 024的FIR滤波器,通过Quartus II 7.1的综合与仿真,以及在EP2S60F1020C4 FPGA目标器件上的实现结果表明,该方法能够有效地减少硬件资源的使用且满足高速实时性的要求。     

Novel Double Modular Redundancy Based Fault-Tolerant FIR Filter for Image Denoising

In signal processing and communication systems, digital filters are widely employed. In some circumstances, the reliability of those systems is crucial, necessitating the use of fault tolerant filter implementations. Many strategies have been presented throughout the years to achieve fault tolerance by utilising the structure and properties of the filters. As technology advances, more complicated systems with several filters become possible. Some of the filters in those complicated systems frequently function in parallel, for example, by applying the same filter to various input signals. Recently, a simple strategy for achieving fault tolerance that takes advantage of the availability of parallel filters was given. Many fault-tolerant ways that take advantage of the filter’s structure and properties have been proposed throughout the years. The primary idea is to use structured authentication scan chains to study the internal states of finite impulse response (FIR) components in order to detect and recover the exact state of faulty modules through the state of non-faulty modules. Finally, a simple solution of Double modular redundancy (DMR) based fault tolerance was developed that takes advantage of the availability of parallel filters for image denoising. This approach is expanded in this short to display how parallel filters can be protected using error correction codes (ECCs) in which each filter is comparable to a bit in a standard ECC. “Advanced error recovery for parallel systems,” the suggested technique, can find and eliminate hidden defects in FIR modules, and also restore the system from multiple failures impacting two FIR modules. From the implementation, Xilinx ISE 14.7 was found to have given significant error reduction capability in the fault calculations and reduction in the area which reduces the cost of implementation. Faults were introduced in all the outputs of the functional filters and found that the fault in every output is corrected.     

Radial basis function networks with FIR/IIR synapses

A learning algorithm for a special class of Radial Basis Functions (RBF) networks is proposed. The novelty aspect of the architecture consists in replacing the usual scalar values of the output weights with linear FIR or IIR filters transfer functions. Simulation results for approximating a lowpass Butterworth filter are presented and other potential temporal processing applications are outlined.