Experimental sync separator and associated circuitry in integrated form

An experimental integrated circuit that performs the functions of sync separation, noise inversion, and AGC amplification was designed and fabricated. The IC uses p-channel enhancement-type MOS units as active transistors, diodes, and resistors. The threshold voltages permit the design of voltage-regulator circuits for the reference levels in the various signal-processing stages. The results of a test of the IC in combination with a commercial TV receiver are described.     

宽带大动态AGC电路设计

自动增益控制电路是接收机模块中的关键控制电路之一,其作用是改善接收机的动态范围。具体分析了自动增益控制电路的工作原理以及AGC的分类方式。为了设计宽带大动态的AGC电路,分析了可变增益ADL5330和对数放大器AD8318的电路功能和主要性标,并利用这两款芯片设计了一种宽带大动态AGC模块,给出了典型电路及测试结果。与传统AGC电路相该电路结构简单、体积小,且能实现宽带、大动态、低噪声放大等功能。     

A robust analog interface system for submicron CMOS video DSP

This paper describes the front-end architecture for a fully integrated low-voltage CMOS video DSP function, including AGC, equalization, clamping, sync, and A/D conversion. With multiple clock domains and many high-activity pads, the large digital section of the IC generates high levels of substrate and power line noise, which cannot be avoided with quiet period sampling. The analog section is therefore designed to minimize the injected noise by other circuit techniques. The system maximizes the available dynamic range in the 3.3-V supply, with several high-bandwidth rail-to-rail functions. A novel arrangement with high noise immunity level estimators is used to clamp the video in the middle of the dynamic range of the input amplifier, hence reducing amplification of unwanted dc components. Extensive mixed signal test facilities are also included in the design. The chip is fabricated in 0.5-μm CMOS, and operates from a single 3.3-V supply     

数字AGC的设计与实现

分析了散射通信系统的特点和AGC的原理,并介绍了2种散射通信中常用AGC电路及其不足之处。然后用VHDL语言设计实现了一种数字AGC电路,此方案采用Altera公司的EP1S40F1020I6芯片,可以实现40dB动态范围的控制,并且具有控制精度高,调节速度快,受环境影响小,稳定性和可靠性高等优点。最后与采用AD8367方案的模拟AGC电路进行联合控制,并进行了实际测试,测试结果表明该设计可以实现65dB动态范围的控制。     

High-PSR sync separator for TV signals

This paper presents a novel NTSC video sync separator (NSS) with a high-PSR (power supply rejection) bias generation circuitry (BGC) which comprises a temperature compensation circuitry. The proposed BGC utilizes step-down regulators and a bandgap-based bias with cascode current control. The clamping voltages required for sync separation from an NTSC signal are generated. Detailed PSR analysis of the proposed BGC is also derived to circumscribe the clamping voltage variation. The proposed design is carried out using 0.35 μm 2P4M CMOS process. The measurement results verify that the HSYNC, the composite signal, and the Line 21 caption data can be separated successfully even if a 1 V noise is coupled in the supply voltage. The measured power consumption of the proposed chip is 31.92 mW.     

大动态范围抗干扰导航接收机AGC 电路性能分析与优化设计

导航接收机的特点是信号比较微弱,通常淹没于噪声以下,其入口电平的波动几乎都由干扰引起。针对这一特点,存在干扰情况下,要求接收机的噪声系数不能显著恶化。射频通道的噪声系数是制约接收机噪声系数的因素之一,本文在给定射频通道噪声系数恶化容限的条件下,以射频通道能实现最大动态范围为优化目标,分析了动态范围及各级电路增益的求解方法;进一步,针对特殊的纯电阻网络AGC 电路,得到了更为简洁的求解方法;最后,本文给出了该类AGC 电路动态范围的设计实例并进行了测试,设计预期与测试结果得到较好的吻合。本文虽然针对导航接收机设计,但可推广应用于指导各类接收机的设计。     

小卫星通信系统射频前端设计

阐述了小卫星的发展背景、工作模式及技术上的优点,介绍了小卫星采用的射频前端系统结构。为了系统的合理设计,以满足星间通信的要求,对系统中低噪放电路、锁相环电路、自动增益控制电路的工作原理和重要指标进行了分析,采用ADS,ADIsimPLL软件仿真,得出适合要求的电路结构。最终制作出系统电路板并调试实现预期指标。     

抗干扰导航接收机射频前端线性度优化设计

针对干扰条件下无自动增益控制(AGC)电路的卫星导航接收机射频前端的设计,在给定A/D采样芯片和混频器的条件下,根据抗干扰需求,提出了线性度指标的优化设计方法,得出了各级电路的增益、1dB压缩点、三阶交调截点和噪声系数的求解方法,以此指导器件选型。根据此优化设计方法,设计了某卫星导航系统的一种接收机射频前端,达到预期抗干扰效果,证明此方法有效可行。     

一种带有外部噪声识别功能的AGC电路的设计

基于红外遥控接收芯片中自动增益控制电路的功能需求及其应用环境,设计了一种能够有效抑制外部环境光干扰、线性度高的自动增益控制电路。该电路在传统自动增益控制电路的设计理念基础上引入外部噪声识别功能,设计的核心子电路包括具有线性增益特性的可变增益放大器、比较器以及利用空闲时间识别外部噪声的信号检测与增益控制电路。电路基于0.25μm标准CMOS工艺设计,使用Hspice软件进行仿真验证。仿真结果表明:电源电压为3~5 V,温度为0~85℃时,可变增益放大器的可控增益范围至少可达-69.5~27.6 dB,且至少具有42 dB的线性增益控制范围。     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

一种新的噪声系数测量方法

测量含有自动增益控制(AGC)电路的射频模块噪声系数时,使用Y因子法将改变模块的功率增益,进而无法测定.本文提出了一种新的噪声系数测量方法.该方法在信噪比较小的条件下用误码率推算前端的载噪比,避免了用仪器标定载噪比受信道滤波器通带平坦性影响较大的问题;测量过程中,AGC输入端信号和噪声的总功率几乎不变,能够保证AGC功率增益不变,从而可准确测量含有AGC电路的射频模块噪声系数.通过理论推导和数值模拟分析了随机误差、系统误差、实验温度以及测量次数对噪声系数估计的影响,验证了方法的有效性.本文成果已用于我国"北斗一号"卫星导航定位用户机的射频模块测量.     

Bipolar monolithic amplifiers for a gigabit optical repeater

Main amplifier, AGC amplifier, and preamplifier ICs have been designed and fabricated using an advanced silicon bipolar process to provide the required characteristics of repeater circuits for a gigabit optical fiber transmission system. The bipolar technology used involved a separation width of 0.3 /spl mu/m between the emitter and the base electrode. New circuit techniques were also used. The differential type main amplifier has a peaking function which can be varied widely by means of DC voltage supplied at the outside IC terminal. A bandwidth which can be varied to about three times the value for a nonpeaking amplifier is easily obtained. The gain and maximum 3-dB down bandwidth were 4 dB and 4 GHz, respectively. The main feature of the AGC amplifier is that the diodes are connected to the emitters of the differential transistor pair to improve the linearity. The maximum gain and 3-dB down bandwidth were 15 dB and 1.4 GHz, respectively, and a dynamic range of 25 dB was obtained. The preamplifier has a shunt-series feedback configuration. Furthermore, a gain and 3-dB down bandwidth of 22 dB and 2 GHz, respectively, were achieved with an optimum circuit design. The noise figure obtained was 3.5 dB.     

快速自动增益控制技术研究

在光电干扰环境中，红外干扰弹辐射能量变化剧烈，抗干扰红外导引头要求实时表征红外干扰弹辐射能量动态变化，以满足幅度鉴别和幅度相关的需要。主放对自动增益控制快速性要求很高。文章介绍了前馈快速自动增益控制电路、计算机增益控制电路工作原理的性能，并对几种自动增益电路性能进行了对比。     

基于晶体管的自动增益控制技术研究

针对传统的自动增益控制方式电路复杂、成本偏高的情况,设计了基于晶体管的自动增益控制方案,包括双晶体管控制方式和单晶体管控制方式,对其工作原理进行了分析。在电路设计环节,推导了基于级联AD603的大动态可变增益放大器(VGA)模型,设计了具体的反馈控制电路。给出了实际电路的测试数据,并对测试结果进行了分析。对这2种控制方式进行了比较,并对特点进行了说明。     

大动态范围AGC电路在接收机中的应用

自动增益控制电路(AGC)是接收机的重要控制电路之一。具体分析了自动增益控制电路的工作原理以及AGC的分类方式。利用可变增益放大器AD8367和其他模拟电路以及外部检波方式,设计了思维简洁、电路控制速度快的峰值型AGC电路。详细解释了芯片版图、增益控制与电压关系以及基于AD8367的闭环AGC电路系统。实验结果表明,基于AD8367的两级AGC控制电路频率达到70 MHz,动态范围80 dB等预期指标,可以方便地调整所需要的输出电平值,确保接收机正常工作。     

Method for switching noise reduction

A method is proposed for reducing digital noise in mixed analogue-digital CMOS circuits. The method is based on a distributed clock driver and reverse clocking technique. It is best suited to circuits where speed can be traded for noise reduction. Reduction factors depend on the circuit design and speed limitations; values in the range 10-50 can be achieved in most cases     

A fully integrated timing generator for the picturephone video-telephone camera

All the timing intervals necessary for a video-telephone camera have been derived from a multivibrator oscillator by a digital process. These include camera blanking, horizontal and vertical sync, sweep triggering, clamp disable, and locked 2:1 interlace. The timing generator consists of a multivibrator and a pulse-delaying circuit using tantalum integrated RC timing elements and silicon integrated circuits. Output signals are derived digitally using resistor-transistor logic, which best meet the requirements of small size, low power, and producibility while providing adequate noise margin. These logic design considerations are discussed. The complete timing generator has been realized using five beam-leaded silicon and two tantalum integrated circuits including 217 transistors, 345 resistors, and capacitors totaling 4000 pF, all mounted on one square inch of ceramic.     

Dual-mode gain control for a 1?V CMOS hearing aid device with enhanced accuracy and energy-efficiency

A dual-mode gain control (DMGC) technique is presented for accurate and energy-efficient pre-amplification in the front-end system of a hearing aid chip. Compared with the conventional automatic gain control (AGC) approach, the DMGC approach is characterized by an amplification switching mechanism between the pro-linearity discrete gain setting mode and the energy-efficient AGC mode. Thus, the total harmonic distortion (THD) should be significantly improved without incurring any degradation concerning other performances parameters (e.g. gain, noise and power consumption). In order to further enhance the system power efficiency, a self current-adapting (SCA) circuit design technique is proposed. Such SCA circuits are capable of automatically adjusting the bias current in accordance with the sound level. A prototype chip was designed with a 0.13???m standard CMOS process and tested with 1?V supply voltage. The measurement results show that, for a typical output level of 500?mV_p-p, the THD is somewhere below ?64?dB, achieving approximately ten times reduction compared to the previously reported works. The power consumption of less than 45???W has also been obtained. In addition, the typical input referred noise is only 2???V_rms and the maximum gain attainable is up to 39?dB.     

小型化AGC模块研制北大核心CSCD

AGC(Automatic Gain Control)模块应用于卫星无线通信系统中,实现中频信号放大以及自动增益控制功能,具有增益高、动态范围大的特点。随着系统小型化需求日益迫切,必须在保持性能和可靠性指标的基础上推进AGC模块小型化。文中首先采用单片电路技术改造混合集成工艺的单元电路,利用E-pHEMT(增强型高电子迁移率晶体管)单片工艺设计了一款电调衰减器及放大器芯片,使单元电路的面积分别缩减至0.9 mm×0.9 mm和0.4 mm×0.6 mm,仅为原单元电路的1/30。通过单元电路与整体电路联合设计优化,在保证整体电路性能的基础上,简化了电路结构,减少了6个元器件。在芯片化改造的基础上,进一步小型化整体电路,使整体电路体积减小了18%。通过上述系列措施,最终将电路体积缩小至18 mm×15 mm×3.5 mm,仅为原电路的1/3且增益和遥测电压性能指标进一步提升。     

高重频激光对激光导引头的干扰机理研究

高重频激光对导引头的干扰涉及到导引头内部自动增益控制(AGC)电路、脉冲展宽电路及信息处理组件等多个部分,频率、能量等因素对不同电路的干扰效果相互影响、叠加,导致对干扰效果的评估复杂。为确定不同影响因素的干扰效果,研究了激光导引头内部电路对激光信号的处理过程,从信号处理的角度分析了高重频激光对激光导引头的干扰机理与干扰效果,并进行了定性验证实验。结果表明,在干扰激光能够进入导引头波门的前提下,高重频激光能量是影响高重频激光对AGC电路及脉冲展宽电路干扰效果的主要因素;在干扰激光能量达到导引头接收阈值的前提下,重复频率是影响高重频激光对信息处理组件干扰效果的主要因素;定性实验在一定程度上验证了机理分析的正确性。