7.5 Gb/s monolithically integrated clock recovery circuit using PLLand 0.3-μm gate length quantum well HEMT's

A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at a bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at a supply voltage of -5 V     

A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver

An 8-Gb/s 0.3-μm CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50°, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2×2 mm² chip consumes 1.1 W at 8 Gb/s with a 3-V supply     

A monolithically integrated 1-Gb/s optical receiver in 1-μm CMOStechnology

Results of a monolithically integrated Si optical receiver for applications in optical data transmission and in optical interconnects with wavelengths of 638 and 850 nm are presented. The optoelectronic integrated circuit (OEIC) implementing a vertical p-type-intrinsic-n-type photodiode achieves a data rate of 1 Gb/s for 638 nm with a sensitivity of -15.4 dBm at a bit-error rate of 10^-9 . The sensitivity of this OEIC in a 1.0-μm CMOS technology is improved by at least a factor of four compared to that of published submicrometer OEICs. A 25-THz.Ω effective transimpedance bandwidth product of the implemented amplifier is achieved     

15 Gbit/s integrated laser diode driver using 0.3 mu m gate length quantum well transistors

An integrated laser diode driver was realised using enhancement/depletion 0.3 mu m recessed-gate AlGaAs/GaAs quantum well transistors. Fully-open eye diagrams were observed at bit rates up to 10 Gbit/s with 50 Omega loads. The maximum DC and modulation current were 25 and 45 mA, respectively. The power consumption is less than 450 mW.<>     

0.3-μm gate length p-channel AlGaAs/InGaAs heterostructure fieldeffect transistors with high cut-off frequency

P-channel Heterostructure Field Effect Transistors (HFETs) with a 0.3-μm gate were fabricated by Mg ion implantation. The maximum transconductance was 68 mS/mm and there was no serious drain or gate leakage current, regardless of this short gate length. The gate turn on voltage (@I_gs=-1 μA/μm) was -2.1 V and its absolute value was large enough for use in complementary HFETs. S-parameters measurements showed a very high cut-off frequency of over 10 GHz. Results indicated the superiority of less-diffusive Mg ion implantation for forming p⁺-layer in p-channel HFETs     

A 1-Gb/s, 0.7-μm CMOS optical receiver with full rail-to-railoutput swing

This paper presents a 1-Gb/s optical receiver with full rail-to-rail output swing realized in a standard 0.7-μm CMOS technology. The receiver consists of a 1-kΩ transimpedance preamplifier followed by a postamplifier based on a biased inverter chain. The latter performs both a linear and a limiting amplification. The automatic biasing of the chain is provided through an offset tolerant replica circuit. The receiver requires no external components or biasing voltages. It is designed for a relatively large 0.8-pF input capacitance and is fed from a single 5-V power supply. These properties make the circuit suitable for a commercial environment. A sensitivity of 10 μA was measured at 1 Gb/s. The complete receiver, including all biasing and replicas, consumes approximately 100 mW from the 5-V supply. When powered from a 3.3-V supply, a maximal bit rate of 600 Mb/s is achieved, while the power consumption is reduced to approximately 26.5 mW     

Approximate optical gain formulas for 1.55-μm strainedquaternary quantum-well lasers

We have used an efficient analytical model to calculate the optical gain of the strained quantum-well laser of InGaAsP-InP material system. Based on the anisotropic effective mass theory, empirical formulas delineating the relations between optical gain, emission wavelength, well width and material compositions are obtained for 1.55-μm In_1-xGa_xAs_yP_1-y quaternary strained quantum-well lasers. Results show a logarithmic relation between the peak optical gain and carrier concentration for all possible material compositions of the quaternary system. We show that the logarithmic relation can be derived algebraically     

1.5-μm InGaAs/InAlGaAs quantum-well microdisk lasers

Microdisk lasers with three InGaAs/InAlGaAs quantum wells were demonstrated for the first time. The selective etching method used to fabricate the laser structure is discussed. Lasers 20 μm in diameter lased with single mode at 1.5-μm wavelength when optically pumped by a pulsed argon-ion laser at 80 K     

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using currentmode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-μm CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors     

20-40 Gb/s 0.2-μm GaAs HEMT chip set for optical data receiver

Using our 0.2-μm AlGaAs-GaAs-AlGaAs quantum well high electron mobility transistor (HEMT) technology, we have developed a chip set for 20-40 Gb/s fiber-optical digital transmission systems. In this paper we describe five receiver chips: a limiting amplifier with a differential gain of 17 dB and a 3 dB bandwidth of 29.3 GHz, a 40 Gb/s clock recovery, a data decision and a 1:4 demultiplexer, both for bit rates of more than 40 Gb/s, and a static 1:4 divider with operating frequencies up to 30 GHz. All presented chips were characterized on wafer with 50-Ω coplanar test probes     

A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter

A serial link transmitter fabricated in a large-scale integrated 0.4-μm CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5:1 multiplexer to reduce the required clock frequency to one-fifth the symbol rate, or 1 GHz. At 5 Gsym/s (10 Gbis), a data eye opening with a height >350 mV and a width >100 ps is achieved at the source. After 10 m of a copper coaxial cable (PE142LL), the eye opening is reduced to 200 mV and 90 ps with pre-emphasis, and to zero without filtering, The chip dissipates 1 W with a 3.3-V supply and occupies 1.5×2.0 mm² of die area     

10-Gb/s driver amplifier using a tapered gate line for improved input matching

The use of a tapered gate line in a distributed amplifier (DA) is investigated and applied to the design of a GaAs monolithic microwave integrated circuit 10-Gb/s optical driver amplifier. Improved input matching is achieved near the cutoff frequency by reducing the characteristic impedance successively along the gate line toward the termination. With the improved matching conditions, the voltage ripple on the final resistor termination is reduced. The degree of tapering that can be employed is limited by the low-frequency gain and matching requirements. Detailed analysis and simulation results are used to investigate the advantage of this technique. To demonstrate its practical use, the performance of a 10-Gb/s DA fabricated with Filtronic Compound Semiconductor's 0.5-/spl mu/m pseudomorphic high electron-mobility transistor technology is presented.     

0.3-μm mixed analog/digital CMOS technology for low-voltageoperation

A 0.3-μm mixed analog/digital CMOS technology for low-voltage operation has been demonstrated, including a new MOSFET structure with laterally doped buried layer (LDB) and a double-polysilicon capacitor with low voltage coefficient. The LDB-structure MOSFET provides constant threshold voltage which is independent of channel length, high current drivability 10% over that of a conventional structure, and low junction capacitance which is less than 1/2 that of the conventional structure. The double-polysilicon capacitor achieves a voltage coefficient of 1/10 that of a conventional capacitor by introducing arsenic ion implantation to the top polysilicon plate and a Si₃N₄ capacitor-insulator, despite the insulator thickness being scaled down to oxide-equivalent 20 nm     

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS,MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-μm CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160×114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-μm CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-Ω strip lines, high-speed signal lines, and 33 power supply layers formed using 50-μm thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80×120×20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection     

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mWbit-interleaved 8:1 multiplexers with a 0.15-μm CMOS technology

This paper reports the first CMOS implementation of an 8:1 byte-interleaved multiplexer (byte-MUX) operating in the Gb/s region, together with an 8:1 bit-interleaved multiplexer (bit-MUX). A future generation 0.15-μm CMOS technology has been applied. Both chips use identical bit-MUX cores with a static shift-register architecture, and have ECL interfaces with a single supply of -2 V. The byte-MUX demonstrates 43-mW/GHz dependence on clock frequency and operates up to 2.8 Gb/s with a power dissipation of 176 mW. The bit-MUX showed 20-mW/GHz dependence on clock frequency and operated up to 3.0 Gb/s with a power dissipation of 118 mW. This revel of performance has been achieved by a novel row-column exchanger configuration, critical path reduction and precise clocking techniques utilized in the bit-MUX core, and the development of high-speed I/O buffers     

Epitaxial liftoff microcavities for 1.55-μm quantum-well spatiallight modulators

Microcavities operating at 1.55 μm have been realized according to the epitaxial liftoff (ELO) technique. The process is described and characterized. No significant variation of the optical properties of the grafted devices has been found. The technique is then applied to a spatial light modulator made by inserting a 3-μm multiple-quantum-well device in a short asymmetric Fabry-Perot microcavity. An enhancement by a factor 1000 of the performances of the switching component is obtained. The input diffraction efficiency reaches 2% in a degenerated four wave mixing configuration with a pulse energy of 1 μJ/cm² and without any applied electric field     

5-Gb/s XOR optical gate based on cross-polarization modulation insemiconductor optical amplifiers

We demonstrate a new design for a XOR optical gate operating in the GHz regime using the cross-polarization modulation effect in a semiconductor optical amplifier. Dynamic and optically controlled polarization rotation in the devices is used to control the output power of the device. Static extinction ratio of the order of 20 dB can be obtained. Bit rate doubling at rate of 1.2 and 2.5 Gb/s have been demonstrated     

Threshold voltage roll-up/roll-off characteristic control insub-0.2-μm single workfunction gate CMOS for high-performance DRAMapplications

Threshold voltage (V_t) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-μm single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N₂ implant prior to gate oxidation is important to reduce V_t roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving V_t roll-off characteristics. Finally, the impact of halo implant on V_t variation in sub-0.2-μm buried channel pFETs is discussed. It is found that halo profile control is necessary for tight V_t variation in sub-0.2-μm single workfunction gate pFET     

InGaAlAs-InP quantum-well infrared photodetectors for 8-20-μmwavelengths

We demonstrate the first long-wavelength quantum-well infrared photodetectors using the lattice-matched n-doped InGaAlAs-InP materials system. Samples with AlAs mole fractions of 0.0, 0.1, and 0.15 result in cutoff wavelengths of 8.5, 13.3, and 19.4 μm, respectively, a 45° facet coupled illumination responsivity of R=0.37 μm and detectivity of D_λ*=3×10⁸ cm·√(Hz)· at T=77 K, for a cutoff wavelength λ_c=13.3 μm have been achieved. Based on the measured intersubband photoresponse wavelength, a null conduction band offset is expected for In_0.52Ga_0.21Al_0.27 As-InP heterojunctions     

1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS

This paper describes the design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. The transmitter is fully compatible (DC coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the voltage-switching principle in order to allow different termination schemes besides the canonical ECL termination, i.e., 50-Ω toward (V_DD-2) V. The addition of some circuit techniques such as dynamic biasing and strobed current switching boosts the dynamic performance of the basic voltage-switching scheme and relaxes the requirements for a high bias current and large-size output devices at the same time. Moreover, thanks to the developed reference circuit, using both feedforward and feedback controls, the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming. The receiver cell is based on a complementary-differential architecture providing high speed and low error on the duty cycle of the CMOS output signal. The integrated receiver-transmitter chain exhibits a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission link using the developed I/O interface was tested up to 1.2 Gb/s