超立方体互连网络中的组播算法研究

在高性能计算中,涉及全局数据迁移、进程控制等操作的通信被称为聚合通信。高效的聚合通信服务不仅能够简化编程,而且能够提高系统效率和整体性能。组播作为聚合通信的通用模式之一,长期以来都是人们的研究重点,包括硬件加速、软件优化、针对不同拓扑结构的研究等。本文研究了超立方体网络中的组播算法,并分析了进一步的研究方向。     

互连网络局部迭代负载平衡技术

新的基于网络的计算模式（如网格计算,云计算,P2P计算）的共同特点是计算节点之间都是通过互连网络进行通信。对互连网络各个计算节点产生的工作负载进行平衡是提高计算系统性能的关键。文章介绍了近年来在互连网络上使用局部迭代方式求解负载平衡问题在算法设计及其性能分析反面的若干基本研究成果。     

Interconnection Networks

Interconnection networks are a natural result of advances in computer technology that brought about demands for improved system performance. As computer systems evolved from the batch-processing models of the 1960's to the time-sharing models of the 1970's, their evolution was basically confined within the von Neumann architectural model, with hardware costs being a significant limiting factor. However, contemporary IC technology is creating an entirely new atmosphere; it is now economically feasible to construct a multiple-processor computer system by interconnecting a large number of off-the-shelf processor and memory modules. In addition, because of today's increased performance requirements, the number of functional modules (homogeneous or heterogeneous) in the multiple-processor system normally keeps rising as the domain of applications grows. Trying to counter this trend presents quite a challenge to computer architects.     

Interconnection Networks Using Shuffles

Networking techniques allow several processors within a multiprocessing system to cooperate efficiently on a single large problem.     

A Kind of Multistage Interconnection Networks with Multiple Paths

1ThisworkwassupportedbytheNationalNaturalScienceFoundationofChina,GralltNo.69473024.1IntroductionMultiprocessorsystemsoftenuseinterconnectionnetworkstoconnectproces-sorsormemorymodules-Atime-sharedbusisthesimplestformofinterconnectionnetworks,butitcannotprovidetheperformancerequiredinmultiprocessorsystemstoday.Acrossbarswitchnetworkisanalternativeusedintheearliersystemstoimplementinterconnection.Theonlydelaytoconnectinputstooutputsisthatofasingleswitchinggate,butacrossbarswitchnetworkisver…     

Interconnection Networks for SIMD Machines

Many SIMD interconnection networks have been proposed. To put the different approaches into perspective, this analysis compares a number of single- and multistage networks.     

Intermittent Fault Diagnosability of Interconnection Networks

An interconnection network’s diagnosability is an important metric for measuring its self-diagnostic capability. Permanent fault and intermittent fault are two different fault models that exist in an interconnection network. In this paper, we focus on the problem pertaining to the diagnosability of interconnection networks in an intermittent fault situation. First, we study a class of interconnection networks called crisp three-cycle networks, in which the cn _in -number (the number of common vertices each pair of vertices share) is no more than one. Necessary and sufficient conditions are derived for the diagnosability of crisp three-cycle networks under the PMC (Preparata, Metze, and Chien) model. A simple check can show that many well-known interconnection networks are crisp three-cycle networks. Second, we prove that an interconnection network S is a t _i -fault diagnosable system without repair if and only if its minimum in-degree is greater than t _i under the BGM (Barsi, Grandoni, and Masetrini) model. Finally, we extend the necessary and sufficient conditions to determine whether an interconnection network S is t _i -fault diagnosable without repair under the MM (Maeng and Malek) model from the permanent fault situation to the intermittent fault situation.     

基于SBC的SIP网络互通的研究

本文讨论了在Firewall和NAT环境下,部署大范围基于SIP的语音和多媒体业务的过程中引发的问题,并就如何在保证用户安全性不受影响的前提下为位于防火墙(Firewall)和网络地址转换(NAT,Network Address Translation)设备之后的终端用户提供业务接入问题进行了研究.然后引出并详细介绍基于会话边界控制(Session Border Control)的SIP多媒体网络安全互通的解决方案,具有较高的实用价值.     

COSI: A Framework for the Design of Interconnection Networks

Editor's note:This article presents a software framework for communication infrastructure synthesis of distributed systems, which is critical for overall system performance in communication-based design. Particular emphasis is given to on-chip interconnect synthesis of multicore designs.—Radu Marculescu, Carnegie Mellon University     

Research Challenges for On-Chip Interconnection Networks

On-chip interconnection networks are rapidly becoming a key enabling technology for commodity multicore processors and SoCs common in consumer embedded systems, the National Science Foundation initiated a workshop that addressed upcoming research issues in OCIN technology, design, and implementation and set a direction for researchers in the field.     

BC互连网络及其性质

提出一种称为一一对应连接（BC）图的互连网络族，使其包含超立方体、交叉立方体和Mobius立方体作为基具子集，同时又使其具有与超立方体、交叉立立体和Mobius立方体相同的对数级的直径和顶点度数、最高连通（容错）度和相同的可诊断性等性质，从而使对超立方体及与其结构相似的大量互连网络的某些性质的研究合而为一，证明了BC互连网络族中包含一类Hamilton连通图并给出了BC互连网族中的图的直径的一个猜想。     

Distributed Diagnosis in Multistage Interconnection Networks

Multistage interconnection networks (MINs) have been widely used in multiprocessor systems and high-speed networks, and the testing of MINs has been investigated by many researchers. However, in previous works the testing results are distributed among all processors, and all those results are needed to diagnose a network. This poses a problem for a truly distributed system where centralized control is not possible. In this paper, a distributed testing and diagnosis scheme for general MINs is discussed. By using the proposed method, concurrent testing and diagnosis of a network can be done by all processors independently, which neither interrupts the normal network operation nor needs any extra hardware.     

On-Chip Interconnection Networks of the TRIPS Chip

The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic. In a 170-million-transistor custom ASIC chip, these NoCs provide system performance within 28 percent of ideal noncontended networks at a cost of 20 percent of the die area. our experience shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.     

Edge Sums Of De Bruijn Interconnection Networks

An interconnection network is a highly symmetrical connected graph of order n nodes, size m edges, connectivity κ and diameter d , where n and κ are large but m and d are small. Many interconnection networks are defined algebraically in such a way that each node has an integer value. Then every edge can be assigned the sum of the two nodes it joins. These numbers are called the edge sums of the graph. The edge sum problem of a graph is to characterize the set of edge sums. This problem was introduced by Graham and Harary who presented the solution for hypercubes. Our object is to characterize the edge sums for another family of interconnection networks, namely, deBruijn graphs.     

Packet Switching Interconnection Networks for Modular Systems

Adding buffers to a packet switching network can increase throughput in certain system architectures. A word of warning—don't make them too large.