共查询到19条相似文献,搜索用时 46 毫秒
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电镀铜导通孔填充工艺 总被引:1,自引:0,他引:1
概述了MacDermid利用电镀铜微盲导通孔填充工艺,可以防止焊接时的孔隙,洞生成和组装时的释气(爆孔),显著的改善了微盲导通孔填充的可靠性。 相似文献
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采用电镀铜充填盲导通孔工艺 总被引:1,自引:0,他引:1
概述了采用电镀铜充填盲导通孔的积层板制造工艺,可以在短时间内完全填充盲导通孔内部,不含残留空隙, 可以获得高导电性和高可靠性的填充盲导通孔。 相似文献
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概述了CuSO4电镀工艺"CU-BRITE TFⅡ"的开发和特性,适用于镀铜层填充导通孔和贯通孔。 相似文献
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随着5G技术的发展,数据传输带宽要求更高,电子元件的功率更大,因此带来封装体的散热负担更重。采用电镀铜填充微通孔在封装载板内形成铜柱阵列散热通道,是一种提高芯片散热效率的常用方式。而在没有优化的电流密度、对流强度和添加剂等各因素条件下电镀微通孔很容易在孔内留下空洞,造成可靠性问题,因此研究各种因素对电镀填孔的影响意义重大。文章通过建立电镀铜填充微通孔的数理模型,并采用多物理场耦合方法分析了微通孔填充的过程和边界条件,得出通孔内电流密度分布情况,实现了对填孔过程的实时模拟。使用电化学工作站对不同种类的添加剂进行恒电流和循环伏安测试,得到不同对流强度下各种类添加剂电化学特性;分析了不同添加剂在孔内调控铜沉积的作用,并给出各添加剂在微通孔处的极化/去极化作用模型。最后,通过哈林槽中测试板电镀研究了电流密度、对流强度、添加剂种类和浓度等重要因素对通孔填充过程的影响和作用,优化出满足工业生产需求的配方及其工艺条件 相似文献
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研究了孔径40μm的硅通孔铜电镀填充工艺,通过改善电镀工艺条件使得孔径40μm、孔深180μm的硅通孔得以填充满。首先,在种子层覆盖以及电镀液相同条件下通过改变电镀电流密度,研究不同电流密度对于铜填充的影响,确定优化电流密度为1ASD(ASD:平均电流密度)。之后,在相同电流密度下,详细分析了超声清洗、去离子水冲洗以及真空预处理等电镀前处理工艺对铜填充的影响。实验表明,采用真空预处理方法能够有效的将硅通孔内气泡排出获得良好的铜填充。最终铜填充率在电流密度为1ASD、真空预处理条件下接近100%。 相似文献
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电子设备的不断轻便化和功能增长的发展趋势推动PCB板朝小型化及线路密度增加的方向发展。传统的过孔(through hole)与导通孔(via)互连的多层PCB板并不是满足这些密度要求的实用解决方法。这促使高密度互连?(HDI)如顺序积层法技术等颠倒是非代方式的引进,同时对微通孔应用的需求也在快速增长,预计这种趋势会不断持续。 相似文献
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概述了下一代电子电路板填充用的CuSO4电镀技术。(1)盲导通孔填充,(2)贯通孔填充,(3)半导体用的凸块和(4)TSV填充。 相似文献
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Investigations regarding Through Silicon Via filling for 3D integration by Periodic Pulse Reverse plating with and without additives 总被引:1,自引:0,他引:1
Lutz Hofmann Ramona EckeStefan E. Schulz Thomas Gessner 《Microelectronic Engineering》2011,88(5):705-708
In this contribution we show experimental investigations regarding Periodic Pulse Reverse (PPR) plating for the filling of Through Silicon Vias that are aimed for the use in 3D integration applications. The purpose of this method is to prevent the use of plating additives that induce high process complexity in terms of process control and high process costs due to the high consumption of those additives. We therefore compare the effect of PPR plating without additives to that effect of PPR plating with additives. In first results with non-optimized PPR plating we already show the large gain in step coverage during TSV filling compared to standard DC plating. 相似文献
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As conventional 2D scaling of microelectronic devices shows limitations, 3D chip stacking is clearly identified as a solution for performance gain at lower cost in applications such as image sensors, stacked memories, high performance processor-memory assemblies and advanced system in package (SiP) leading to heterogeneous integration. In that respect, Through Silicon Via (TSV) technology is one on the key process step to enable new interconnection schemes. Metallization of TSV structures is currently attracting a lot of attention due to the multiple technical challenges associated with this new technology [K. Kondo, T. Yonezawa, D. Mikami, T. Okubo, Y. Taguchi, K. Takahashi, D.P. Barkey, J. Electrochem. Soc. 152 (2005) H173; O. Lühn, C. Van Hoof, W. Ruythooren, J.-P. Celis, Electrochim. Acta 2007, doi:10.1016/j.electacta.2008.04.002]. Copper electrodeposition has soon been identified as a technique of choice for such connections based on the widely acceptance of copper as wiring material for submicronic interconnections [T.P. Moffat, D. Wheeler, M. Edelstein, D. Josell, IBM J. Res. Dev. 49 (2005) 19; J. Reid, Jpn. J. Appl. Phys. - Part 1 40 (2001) 2650]. However, the specificity of TSV structures, combining both high aspect-ratios and via depth ranging from tenth to several hundred microns, implies the development of new deposition methodologies and chemistries. In particular, the mode of action of organic additives (accelerator, suppressor and leveller) promoting the so-called “bottom-up filling” can be greatly affected by mass transportation and convection effects associated with large volumes TSV vias compared to Damascene structures.Here we present a study aiming at optimizing the accelerator concentration in the plating bath in order to maximise the copper deposition rate while preserving a reduced overburden at the via mouth. Cyclic voltammetry data correlated with filling experiments conducted on 150 μm vias with an aspect-ratio of 2, will be presented in order to better understand the relationship between chemical composition and process efficiency in such TSV structures. 相似文献