A new structure of substage in pipelined analog-to-digital converters

The article presents a new (1+1)-bit/stage structure for pipelined analog-to-digital converters (ADC). When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators' decision levels. The ADC implemented in Semiconductor Manufactory International Corporation (SMIC) 0.18 μm CMOS process consumes 210 mW and occupies a chip area of 3.2×3.7 mm2.     

Digital background calibration for memory effects in pipelined analog-to-digital converters

Memory errors can occur in the stages of a pipelined analog-to-digital converter (ADC) due to several effects. These include capacitor dielectric absorption/relaxation, incomplete stage reset at high clock rates, and parasitic capacitance effects when opamps are shared between subsequent pipeline stages. This paper describes these sources of memory errors and the effect they have on overall ADC linearity. It is shown how these errors relate to and differ from interstage gain errors. Two new calibration algorithms are proposed that correct for memory errors by digital post-processing of the ADC output. Both algorithms operate in the background and so do not require conversion to be interrupted in order to track changes due to temperature and supply variations. The two algorithms are compared in terms of their system costs and their dependence on input signal statistics.     

Calibration technique for SAR analog-to-digital converters

A self-calibration technique was developed for SAR analog-to-digital converters that employ binary-weighted capacitors. High-accuracy calibration is achieved by finding and correcting the mismatch of each capacitor independently. The mismatch errors are extracted at power-up, and corrected by individual calibration DACs during the conversion. Unlike in previous schemes, in the proposed method the residual error in the calibration of a capacitor does not affect the calibration of any other capacitor. Simulation results show that the proposed method is also insensitive to the non-idealities of the calibration DACs.     

New current-mode wave-pipelined architectures for high-speed analog-to-digital converters

In this paper, two new architectures for high-speed CMOS wave-pipelined current-mode A/D converters (WP-IADCs) are proposed and analyzed. In the new WP-IADC architectures, the wave-pipelined theory is applied to both pipeline structures, called full WP-IADC (FWP-IADC) and indirect transfer WP-IADC (ITWP-IADC). In the FWP-IADC, each stage uses the full current-mode wave-pipelined structure without switched-current cell circuits. In the ITWP-IADC, the switched-current cells are incorporated into the wave-pipelined stages which are divided into several sections with controlled clocks. Therefore, the proposed ITWP-IADC performs optimally in terms of speed and accuracy in the WP-IADCs. Generally, the proposed WP-IADCs have the advantages of high speed, high input frequency, high efficiency of timing usage, high clock-period flexibility in switched-current cells for precision enhancement, and reduced number of switched-current cells in the overall data path for linearity improvement. According to the theoretical analysis on the proposed WP-IADC structures, the minimum sampling clock period is proportional to the intrinsic delay of the current mirror and the increased rise/fall time in each wave-pipelined stage. The HSPICE simulation results reveal that, under Nyquist rate sampling in 8-b resolution, a sampling rate of 20 and 54 MHz can be achieved for FWP-IADC and two-section ITWP-IADC, respectively. If four wave-pipelined sections are used, the ITWP-IADC can be operated at 166 MHz at an input frequency of 8 MHz. To experimentally verify the correct function of the proposed WP-IADC structures, the proposed new architecture of the FWP-IADC is implemented by using 0.35-/spl mu/m CMOS technology. The measurement results successfully demonstrate the feasibility of wave-pipelined IADC architectures in applications of high-speed ADCs.     

A background comparator calibration technique for flash analog-to-digital converters

This paper presents a background calibration technique for trimming the input-referred offsets of the comparators in a flash analog-to-digital converter (ADC) without interrupting the ADC's normal operation. For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. Binary feedback is then used to digitally adjust the comparator's offset so that the offset is minimized. All calibration procedures are performed in the digital domain. The calibration performance is characterized by the converging speed of the feedback loop and the offset fluctuation due to the disturbance of the ADC's input. These two performance indexes of a background-calibrated comparator (BCC) are determined by three parameters: the probabilistic distribution of the ADC's input, the BCC's offset quantized step size, and the threshold of an internal bilateral peak detector. The offset fluctuation of a BCC can be drastically reduced by employing a windowing mechanism. The use of windowed BCCs in a flash ADC can introduce nonmonotonic-threshold (NMT) effects which include an increase in calibration settling time and an increase in /spl sigma/(V/sub OS/). The use of uncorrelated random chopping for neighboring BCCs can ensure the validity of offset detection and mitigate the NMT effects.     

A background timing-skew calibration technique for time-interleaved analog-to-digital converters

This paper presents a background timing-skew calibration technique for time-interleaved analog-to-digital converters (ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by counting the number of zero crossings of the ADCs input while randomly alternating their sampling sequence. Digitally controlled delay units are adjusted to minimize the timing skews among the A/D channels caused by the mismatches among the clock routes. The calibration behaviors, including converging speed and timing jitter, are theoretically analyzed and verified with simulations. A 6-bit 16-channel ADC is used as an example.     

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-/spl mu/m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V/sub p-p/ differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.     

Averaging technique in flash analog-to-digital converters

The averaging technique is used in flash analog-to-digital converters to reduce nonlinearities resulting from random offset voltages of the pre-amplifiers, which stand before the comparators. The main contribution of this paper is to provide further insight into this technique, through exact closed-form expressions obtained for the output voltage, gain, integral nonlinearity and differential nonlinearity in averaged pre-amplifiers. These theoretical results are compared with HSPICE simulations, and a very good agreement is found. Finally an automatic design procedure is described, which is based on the expressions derived, and a design example is given.     

Least mean square adaptive digital background calibration of pipelined analog-to-digital converters

We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors including capacitor mismatch, finite op-amp gain, op-amp offset, and sampling-switch-induced offset, provided they are not signal-dependent. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques.     

高速光学模数转换器的研究现状及进展

高速高精度模数转换器（Analog-to-digital Converters,ADC）是现代数字信息处理系统中的关键组成部分,现有的电子模数转换器存在运行速率严重受限的难题,因此引入光学方法实现高速高精度模数转换成为研究的热点。本文重点针对高速光学模数转换器的研究现状及进展进行了探讨,并对光学辅助、光采样电量化、电采样光量化以及全光采样量化目前4种最主要的光学模数转换器的原理、结构和最新的研究进展进行了详细的介绍。     

Parallel correlated double sampling technique for pipelined analogue-to-digital converters

A new correlated double sampling technique that avoids the additional thermal noise penalty is presented. The new technique employs a low- gain two-stage opamp with the second stage made up of multiple gain stages in parallel. The superior noise performance of the proposed technique to correlated double sampling is shown.     

A low-power reconfigurable analog-to-digital converter

A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta-sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phase-locked loop (PLL). This converter also incorporates several power-reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0-10 MHz over a resolution range of 6-16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta-sigma mode, it achieves a maximum signal-to-noise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of ±0.55 LSBs and ±0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with 24.6 mW of power     

Digital based calibration technique for continuous-time bandpass sigma-delta analog-to-digital converters

In this paper, a calibration technique for Noise Transfer Function (NTF) optimization of Continuous-Time Bandpass Sigma Delta (CT BP ΣΔ) modulators is presented. The proposed technique employs a test tone applied at the input of the quantizer to evaluate the noise transfer function of the Analog-to-Digital Converter (ADC) using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed-mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal-to-Quantization Noise Ratio (SQNR) performance is extracted via an LMS software-based algorithm. Simulation results show that notch frequency of the NTF due to process variations and temperature tolerances can be tuned using the proposed methodology. The proposed global calibration approach can be used during the system start-up and the idle system time. The proposed approach uses a single in-band calibration tone, but it can be expanded using out-of band test tones for background calibration schemes.     

An efficient power reduction technique for CMOS flash analog-to-digital converters

An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. The presented technique adopts the procedure with a simple coarse comparison first followed by a finer comparison later. Our ADC design does not decrease the total number of comparators, though it is able to reduce the power consumption. Subject to time signal controlling, the manipulation is to interchangeably shut down the comparator sections for the coarse comparison function. Experimental results show that this new method consumes about 48.14 mW at 400 MHz with 3.3 V supply voltage in TSMC 0.35 μm 2P4 M process. Compared with the traditional flash ADC, our low power method can reduce up to 47.8% in power consumption. The DNL of our proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the ENOB is 5.75 bits. The chip area occupies 0.4 × 0.9 mm² without I/O pads.     

A survey on nonlinear analog-to-digital converters

This paper presents a survey on Nonlinear Analog-to-Digital converters (ADC). This class of converters is extremely relevant in applications where there is a need for non-uniform quantization characteristic, for example, some specific applications in the areas of light detection, hearing aid, nuclear physics, image acquisition, communication systems, etc. This survey outlines the state-of-the-art Nonlinear ADC topologies, such as, floating point, logarithmic, piecewise linear and oversampled nonlinear converters, and discusses their performance and advantages in terms of their applications.     

A new on-chip digital BIST for analog-to-digital converters

A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminates the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using Mitel CMOS 1.5 μm technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converters or high resolution pipelined analog-to-digital converters. The presented BIST shows satisfactory results for a nine-bit pipe-lined analog-to-digital converter.     

A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion

A cascade of sigma-delta modulator stages that employ a feedforward architecture to reduce the signal ranges required at the integrator inputs and outputs has been used to implement a broadband, high-resolution oversampling CMOS analog-to-digital converter capable of operating from low-supply voltages. An experimental prototype of the proposed architecture has been integrated in a 0.25-/spl mu/m CMOS technology and operates from an analog supply of only 1.2 V. At a sampling rate of 40 MSamples/sec, it achieves a dynamic range of 96 dB for a 1.25-MHz signal bandwidth. The analog power dissipation is 44 mW.     

A new pipelined analog-to-digital converter using current conveyors

A new pipelined analog-to-digital converter (ADC) using second-generation current conveyor (CCII) is presented. Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCII instead of operational amplifier (OA). Experimental results show that the proposed CCII-based pipelined ADC can work at 12.5 MHz with a 7.3-bit resolution. The DNL is within −0.4 LSB and 0.4 LSB and INL is within −0.8 LSB and 0.8 LSB, respectively. The pipelined ADC is realized in TSMC 0.35 μm CMOS technology and consumes 29 mW under a 3.3 V power supply. The core size is 0.85×0.85 mm². Sing-Yen Wu received the M.S. degree in the Department of Electronic Engineering from National Taipei University of Technology, Taipei, Taiwan, in 2005. His current research interests include CMOS pipelined analog-to-digital converters and mixed-signal integrated circuit. Lu-Po Liao received the M.S. degree in the Department of Electronic Engineering from National Taipei University of Technology, Taipei, Taiwan, in 2003. His current research interests include analog integrated circuit design and mixed-signal integrated circuit design. Chia-Chun Tsai received the Ph.D. degrees in Electrical Engineering from National Taiwan University, Taipei, Taiwan, 1991. From 1989 to 2005, he served at the Department of Electronic Engineering, National Taipei University of Technology, Taipei, Taiwan. Since 2005 he has been with the Department of Computer Science and Information Engineering, Nanhua University, Chiayi, Taiwan, where he is a Full Professor. His current research interests include VLSI design automation and mixed-signal IC designs.     

An efficient background calibration technique for analog-to-digital converters based on neural network

This paper introduces a background digital calibration algorithm based on neural network, which can adaptively calibrate multiple non-ideal factors in a single-channel ADC, such as gain error, mismatch, offset and harmonic distortion. It enables an efficient background calibration through a simple feed forward neural network and LM gradient descent algorithm. The simulation results show that in the case of a signal input close to the Nyquist frequency, for a 14-bit 500 MS/s prototype ADC, only about 40,000 data needed, the ENOB of the ADC can be increased from 7.81 to 13.06 and the SFDR from 49.7 dB to 106.8 dB assisted by a lower speed reference ADC.     

A novel low-voltage operational amplifier for low-power pipelined ADCs

A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.