名词术语释义：无铅化封装

集成电路的封装主要是采用锡铅焊料，含铅器件再利用过程中有毒物质将对环境产生污染。焊料的无铅化是无铅封装的关键，目前较为常用的封装无铅化主要是通过无铅焊膏来实现。     

真空炉金锡封焊

文章在介绍半导体金锡焊料封装工艺的基础上,重点对金锡焊料、炉温曲线设置等工艺技术问题进行了深入研究。基于大量的金锡焊料真空焊接封装实验及理论分析,研究了器件气密封装技术。讨论了封焊夹具、管帽镀层、合金状态、封接面表面、压块、焊料厚度以及加热程序对焊接质量的影响。密封后的产品在经过环境试验和机械试验考核后,封装气密性能很好地满足要求。并且结合应用背景证明了所采用的合金及封装工艺的可行性。     

基于共晶焊接工艺和板上封装技术的大功率LED热特性分析

采用ANSYS有限元热分析软件,模拟了基于共晶焊接工艺和板上封装技术的大功率LED器件,并对比分析了COB封装器件与传统分立器件、共晶焊工艺与固晶胶粘接工艺的散热性能。结果表明:采用COB封装结构和共晶焊接工艺能获得更低热阻的LED灯具;芯片温度随芯片间距的减小而增大;固晶层厚度增大,芯片温度增大,而最大热应力减小。同时采用COB封装方式和共晶焊接工艺,并优化芯片间距和固晶层厚度,能有效改善大功率LED的热特性。     

塑封碳化硅肖特基二极管粘片工艺

粘片工艺是塑封碳化硅肖特基二极管封装中的关键工艺,实现了芯片背面金属与引线框架的物理连接与电连接,对器件的参数以及可靠性影响较大。我们发现器件生产中或者器件可靠性的多种失效模式都产生于粘片工艺。我们通过对焊料成分、拍锡头结构,工艺参数的优化等,使器件的品质大大提升。     

适用于大批量晶圆和基底凸起工艺的焊球置放及印刷和回流焊技术

1前言 市场对于芯片级封装(CSP)的需求正在迅速增长,CSP封装是指封装器件的尺寸最多比芯片本身的尺寸大20%.晶圆级CSP是最普遍的芯片级封装形式之一,其焊料凸起或焊球直接沉积在硅晶的电阻接点上.     

高可靠电子产品中3D-plus器件装配工艺可靠性研究

与传统的表面贴装器件相比,3D-plus封装形式的器件Z向尺寸较大、重心较高,影响器件的力学适应性。其特殊的封装工艺带来了引线搪锡、焊接及防护等诸多工艺困难。介绍了3D-plus封装器件的结构工艺特点。总结了该类器件电装全过程中的实施工艺。通过开展相关的工艺可靠性试验,证明在现有的工艺条件下采用目前的实施工艺能够满足产品的高可靠性实施要求。     

镍金表面上LP封装中央焊盘焊点空洞控制

随着产品小型化的发展,微小LP封装器件的应用越来越广泛,其中中央焊盘焊点空洞率成为影响产品功能的关键因素.主要研究镍金表面处理印制电路板上LP封装器件中央焊盘锡铅焊点空洞问题.介绍了焊点空洞的产生机理、焊接工艺难点及空洞控制方法,提出了优化焊盘设计、优化模板开孔设计、强化焊膏使用控制、控制焊膏印刷精度、控制贴装精度和优化焊接工艺参数等六大保证措施.经试验验证,同时采取6项措施后,有效地控制了镍金表面处理的PCB上LP封装器件的中央焊盘焊点空洞问题.     

超大面积芯片烧结技术研究

随着半导体大功率器件的发展,芯片的散热一直是制约功率器件发展的因素之一。而器件内部散热主要是通过芯片背面向外传导,芯片焊接工艺是直接影响器件散热好坏的关键因素之一,合金焊料的一个显著优点就是其导热性能好,因此在散热要求高的大功率器件中使用较为广泛(如Au80Sn20、Au99.4Sb0.6等),但由于合金焊料烧结后会产生较大的残余应力,在尺寸大于8 mm×8 mm的芯片上,烧结工艺应用较少。文章针对11.5 mm×11.5 mm超大面积芯片进行金锡合金烧结试验,经过对应力产生的原因进行分析,从材料、封装工艺等方面采取措施来降低缓释应力,并对封装产品进行可靠性考核验证。试验结果表明,没有芯片存在裂纹、碎裂现象,产品通过了可靠性验证。     

热学环境下2.5D封装器件60Pb40Sn互连焊点可靠性研究

2.5D封装具有信号传输快、封装密度高等特点,被广泛应用于高性能集成电路封装工艺中。目前2.5D器件在互连焊点方面通常采用无铅焊料,不满足宇航用器件含铅量不低于3%的要求。采用60Pb40Sn焊料作为2.5D封装器件中硅转接基板与上层芯片之间互连焊点,评估了60Pb40Sn焊点的互连可靠性,结果显示器件在1000次-65～150℃温度循环、1000 h 150℃稳定性烘焙、500次-65～150℃热冲击后互连合格,初步证实了60Pb40Sn焊料在2.5D封装器件应用的可行性。     

PoP叠层封装的组装工艺（下篇）

作者汇集国际会议相关外文论文,结合作者在华为等企业的工作实践,撰写此文,供同行参考。本文介绍了PoP（PackageonPackage）叠层封装的基本结构,SMTI艺模式和SMT组装工艺过程,重点介绍了PoP叠层封装的助焊剂／锡膏的浸蘸工艺过程,介绍了浸蘸锡膏材料及浸蘸锡膏的特性要求,PoP再流焊温度曲线的设定,对预制PoP和在板PoP热循环疲劳结果分析。从底部填充材料选择、填充空洞、底部填充可靠性3个方面介绍YPoP器件的底部填充效果和工艺。介绍To．4mm细间距PoP器件的SMT组装工艺过程,及相关工艺参数的设定。介绍了0．4mm穿透模塑通孔（TMV）结构PoP器件的空气气氛下的再流焊工艺过程及相关工艺参数的设定。从对焊接缺陷、PoP封装各层状况和翘曲测量方面来介绍如何进行PoP器件的×射线检测。从共面性和高温翘曲、温度循环、跌落冲击和弯曲疲劳4个方面介绍了0．4mmPoP器件的可靠性。本文最后介绍了PoP器件的清洗。     

VDMOS器件贴片工艺中气泡的形成机制与影响

功率MOS管的封装贴片工艺会在贴片层中引入气泡,从而严重降低器件的机械性能、热性能和电学性能.本研究就VDMOS管D-PAK封装模式,给出了贴片工艺中气泡的产生机制及其影响,并利用FEA方法建立了其D-PAK封装的热学模型.根据模拟结果,在贴片层中气泡含量提高时,热阻会急剧增大而降低器件的散热性能.     

车载IGBT器件封装装片工艺中空洞的失效研究

IGBT芯片在TO-220封装装片时容易形成空洞,焊料层中空洞大小直接影响车载IGBT器件的热阻与散热性能,而这些性能的好坏将直接影响器件的可靠性。文章分析了IGBT器件在TO-220封装装片时所产生的空洞的形成机制,并就IGBT器件TO-220封装模型利用FEA方法建立其热学模型,模拟结果表明:在装片焊料层中空洞含量增加时,热阻会急剧增大而降低IGBT器件的散热性能,IGBT器件温度在单个空洞体积为10%时比没有空洞时高出28.6℃。同时借助工程样品失效分析结果,研究TO-220封装的IGBT器件在经过功率循环后空洞对于IGBT器件性能的影响,最后确立空洞体积单个小于2%,总数小于5%的装片工艺标准。     

Soft solder die bonding of multiple die devices

The aim of the work presented in this paper is to study the soft solder die attach of multiple die devices by a multiple pass process. With a multiple pass process we mean a procedure which needs as many die bonder furnace passes as there are different types of dice to be bonded into a package. The main focus of the investigation is on the effect of the necessary multiple furnace passes on the reliability of the soft solder attachment layer. As this behavior may depend on the specific type of device or package (i.e., solder alloy-substrate combination, die size, package geometry), it is analyzed relative to the one of an identical die processed in one single furnace pass. A real package (TO-220) is used as test vehicle and processed on standard equipment. A detailed analysis of the multiple pass process relative to a single pass process with appropriate equipment is performed. It is concluded that a multiple pass process may be slightly less efficient for throughput. However it gives more process flexibility and allows using standard equipment which is available on the market. The result of this investigation strongly supports the feasibility of multiple die devices with a multiple pass process. No reliability limiting influence of the additional furnace passes causing a repeated re-melting and re-solidifying of the solder layer is found. It is, however, necessary to investigate the capability for any other specific device or package again     

粘结层空洞对功率器件封装热阻的影响

功率器件的热阻是预测器件结温和可靠性的重要热参数,其中芯片粘接工艺过程引起的粘结层空洞对于器件热性能有很大的影响。采用有限元软件Ansys Workbench对TO3P封装形式的功率器件进行建模与热仿真,精确构建了不同类型空洞的粘结层模型,包括不同空洞率的单个大空洞和离散分布小空洞、不同深度分布的浅层空洞和沿着对角线分布的大空洞。结果表明,单个大空洞对器件结温和热阻升高的影响远大于相同空洞率的离散小空洞;贯穿粘结层的空洞和分布在芯片与粘结层之间的浅空洞会显著引起热阻上升;分布在粘结层边缘的大空洞比中心和其他位置的大空洞对热阻升高贡献更大。     

贴片焊层厚度对功率器件热可靠性影响的研究

贴片工艺是用粘接剂将芯片贴装到金属引线框架(一般是由铜制成)上的过程.富铅的Pb/Sn/Ag软焊料在功率器件封装贴片工艺中作为粘接剂应用十分广泛.从功率器件整体来看,贴片焊层毫无疑问是影响器件可靠性最重要的因素之一,其不仅具有良好的导电导热性能,而且该焊层能够吸收由于芯片和引线框架之间的热失配而产生的应力应变,保护芯片免于受到机械应力的损伤.基于Darveaux的热疲劳寿命分析模型,利用功率循环加速实验以及有限元方法具体分析了贴片焊层厚度BLT对于功率器件热可靠性的影响.并通过实验与仿真的结果,提出提高功率器件热可靠性的设计原则.     

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.     

形成倒装芯片焊点的铜接线柱焊凸(SBC)法

在倒装芯片应用中生长晶圆焊凸的工艺中对于间距较小(即小于150μm)、具有数个尺寸为150μm的焊凸,倒装前的焊锡涂敷好坏对产品的良率和可靠性起着重要作用。因为,如果涂敷的焊锡体积不均匀,就经不起涂敷过程中为确保涂敷在引线框上焊锡的完整和体积一致性而引入的强制视像系统检查,从而降低产出率。这就是一些组装工艺正设法减少或取消这些限制的原因。另一方面,采用直接熔化焊凸的方法来形成焊点是一种速度较快的工艺,但在保证回流处理后的离板高度方面有缺点,导致在温度和功率循环测试中的表现较差。介绍的采用铜接线柱焊凸(SolderBumponCopperStud;SBC)法解决了这些问题;对于那些需要倒装的组装工艺而言,这是可保障其制造性较佳的解决方案。介绍采用铜接线柱焊凸(SBC)工艺在附着在倒装芯片上的金属基片和焊凸之间形成焊点的新方法,利用铜接线柱焊凸技术再配合晶圆级的焊锡丝印工艺在半导体上预先形成焊凸。这是替代电镀焊凸工艺一种别具成本效益的方法。     

Characterization of chip scale packaging materials

The mechanical stability of Chip Scale Packages (CSP) used in surface mount technology is of primary concern. The dominant issues are package warpage and solder fatigue in solder joints under cyclic loads. To address these issues, molding compound and die attach film were characterized with finite element method which employed a viscoelastic and viscoplastic constitutive model. The model was verified with experiments on package warpage, PCB warpage and solder joint reliability. After the correlation was observed, the effect of molding compound and die attach film on package warpage and solder joint reliability was investigated. It was found that package warpage tremendously affected solder joint reliability. Furthermore, a die attach film was developed based on results of the modeling. CSP with the developed die attach film are robust and capable of withstanding the thermal stresses, humidity and high temperatures encountered in typical package assembly and die attach processes. Also, a lead free solder is discussed based on the results of creep testing. This paper presents the viscoelastic and viscoplastic constitutive model and its verification, the optimum material properties, the experimental and simulated reliability and performance results of the u*BGA packages, and the lead free solder creep.     

Mechanical, thermal, and electrical analysis of a compliant interconnect

Ball grid array (BGA) package styles use solder balls as electrical interconnects between packages and application boards. Solder balls are rigid and tend to fracture under thermal fatigue and/or shock loading. Metalized polymer spheres (MPS) offer a more compliant interconnect, compared to solder balls, thereby increasing the thermal cycling fatigue life. A reduction in thermal and electrical performance may be expected for MPS interconnects as a result of its higher thermal and electrical resistances. A 5% and an 8% increase in MPS thermal resistance was measured for a carrier array ball grid array (CABGA) package and a plastic ball grid array (PBGA) package, respectively, compared to eutectic solder balls. However, this small reduction was offset by large gains in the solder joint life. A 1.6 times increase in the mean thermal fatigue life was measured for a CABGA using MPS interconnects compared to eutectic solder balls. A first-order model showed that eutectic solder balls provide greater process margins, compared to MPS interconnects, due to the ball collapse during reflow.     

Assessment of Thermomechanical Damage of Electronic Parts Due to Solder Dipping as a Postmanufacturing Process

Tin whiskering is a concern with tin-rich alloy finishes on electronic part terminations. Solder dipping may be used to replace the original finish with eutectic tin-lead solder for tin-whiskering risk mitigation purposes. However, the solder dipping process may expose electronic parts to thermomechanical damage within the package due to the thermal refinishing profile used during dipping. This paper discusses solder dipping as a refinishing technique and the associated risks from thermomechanical damage. An experimental study was used to assess the possibility of thermomechanical damage on various electronic part-types of different package configurations. Package and die geometries were characterized for all part-types to develop quantitative metrics, which may be used by electronic part users to assess parts for their susceptibility to thermomechanical damage.