Analytical threshold voltage model for short channeln+-p+ double-gate SOI MOSFETs

Solving a two-dimensional (2-D) Poisson equation in the channel region, we have developed models for short channel n⁺-p⁺ double-gate SOI MOSFETs, and showed how to design a device with a decreased gate length, suppressing short channel threshold voltage shift ΔVth and subthreshold swing (S-swing) degradation. According to our model, we can design a 0.05 μm L_G device of which threshold voltage is 0.2 V, ΔVth is 25 mV, and S-swing is 65 mV/decade with a 3-nm-thick gate oxide and 12-nm-thick SOI     

Retention characteristics of hole-injection-type EEPROM

The retention characteristics of FAMOS-type EEPROM using avalanche injection of holes for ERASE operation were analyzed. The avalanche-injected holes into the SiO2gate oxide are likely to be trapped at the defects in the gate oxide before arriving at the floating gate. Some samples show that the threshold-voltage shift due to trapped holes versus the threshold voltage shift due to the total holes injected into the oxide comes up to 80 percent. The retention characteristics of trapped holes are poor. By detrapping these holes, the drain voltage of a FAMOS-type device is increased. The resultant acceleration of the unintentional writing due to the channel current-induced hot electrons may be a dominant factor in the retention characteristics.     

GeSiMOSFET的纵向结构对器件性能的影响

为了研究器件参数对GeSi MOSFET器件性能的影响,本文在建立一个简单的GeSi MOSFET的器件模型的基础上,对GeSi MOSFET的纵向结构进行了系统的理论分析.确定了纵向结构的CAP层厚度、沟道层载流子面密度、DELTA掺杂浓度以及量子阱阱深之间的关系,得出了阈值电压与DELTA掺杂浓度、栅氧化层厚度及CAP层厚度之间的关系,还得出了栅压与沟道载流子面密度、栅氧化层厚度及CAP层厚度之间的关系.并且在此基础上得出了一些有意义的结果.为了更细致、精确地进行分析,我们分别对GeSi PMOSFET和GeSi NMOSFET在MEDICI上做了模拟.     

Stacked gate mid-channel injection flash EEPROM cell. I.Programming speed and efficiency versus device structure

Presents a new flash EEPROM cell which has been fabricated to achieve fast programming with low power. This memory cell attains speed and efficiency, comparable to the split-gate device, while preserving a simple stacked gate structure. The device programs faster than the stacked gate cell by a factor of about ten. Also, the threshold voltage shift of 5 V can be accomplished with the drain voltage of 3 V in about 50 μs. The proposed memory cell is strongly resistant against the punchthrough effect and is capable of erasure in byte unit at the drain side. Factors pertinent to programming are discussed, theoretically and experimentally, in correlation with device structures. The hot electron dwell time in the channel is shown to be an important parameter, affecting the programming speed and efficiency     

Stacked gate mid-channel injection flash EEPROM cell-Part II:analysis of gate current and modeling of programmingcharacteristics

The programming characteristics of the stacked gate mid-channel injection (SMCI) flash memory cell is quantitatively analyzed vis a vis the stacked gate device. In the present model, the hot electrons in the high field channel region are described by the elevated temperature model. The programming speed and efficiency depend, among other factors, on the carrier lifetime, which is limited by both the recombination process and the carrier dwell time in the channel. The gate currents from the reference devices are quantitatively analyzed and specified empirically via the applied voltages and the device parameters. These results are applied to modeling the shift in time of the threshold voltage and the simulated values are shown to fit the data with a fair degree of accuracy     

Total ionizing dose effect in 0.2 μm PDSOI NMOSFETs with shallow trench isolation

This paper presents the total ionizing dose radiation performance of 0.2 μm PDSOI NMOS devices under different bias conditions. The hump effect is observed in the transfer characteristic of the back gate device instead of the front gate device after radiation. A STI bottom corner parasitic transistor model is proposed to explain this phenomenon. It also provides a simple way to extract the effective sheet charge density along the STI sidewall. Three-dimensional simulation was applied to explain the radiation effect. It shows that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide where the STI and the BOX are connected, is the dominant contributor to the off-state drain-to-source leakage current. The dimension of the transistor plays an important role on influencing the device’s performance after radiation. Larger off-state leakage current and radiation induced threshold voltage shift are reported in the narrow channel device than in the wide channel one. Different TID responses due to the STI process variation are also discussed.     

Analytical model for threshold voltage shift due to impuritypenetration through a thin gate oxide

We derived an analytical model for the threshold voltage shift due to impurity penetration through gate oxide and evaluated the thermal budget for pMOS devices with a thin gate oxide. The threshold voltage shift decreases as the channel doping concentration increases, but the decrease is quite small. The allowable surface concentration of the penetrated impurity increases as the gate oxide thickness decreases if the allowable threshold voltage shift is constant. Therefore, the allowable diffusion length normalized by the gate oxide thickness d_ox increases with decreasing d_ox     

Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

Analysis of different parameters of channel material and temperature on threshold voltage of CNTFET

Carbon nanotubes have some unique features and special properties that offer a great potential for nano-electronic devices. In this paper, we have analyzed the effect of chiral vector, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage of CNTFET over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as of MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime especially when the gate length is around 10 nm; which is quite contrary to the well known short channel effects in MOSFET. It is observed that at or below 10 nm channel length the threshold voltage increases rapidly in case of CNTFET device whereas in case of MOSFET device the threshold voltage decreases drastically.     

An analytical back gate bias dependent threshold voltage model forSiGe-channel ultrathin SOI PMOS devices

An analytical threshold voltage model for SiGe-channel ultrathin SOI PMOS devices is presented. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical-formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide     

Comparative study of leakage power in CNTFET over MOSFET device

A comparison of the CNTFET device with the MOSFET device in the nanometer regime is reported.The characteristics of both devices are observed as varying the oxide thickness.Thereafter,we have analyzed the effect of the chiral vector and the temperature on the threshold voltage of the CNTFET device.After simulation on the HSPICE tool,we observed that the high threshold voltage can be achieved at a low chiral vector pair.It is also observed that the effect of temperature on the threshold voltage of the CNTFET is negligibly small.After that,we have analyzed the channel length variation and their impact on the threshold voltage of the CNTFET as well as MOSFET devices.We found an anomalous effect from our simulation result that the threshold voltage increases with decreasing the channel length in CNTFET devices; this is contrary to the well known short channel effect.It is observed that at below the 10 nm channel length,the threshold voltage is increased rapidly in the case of the CNTFET device,whereas in the case of the MOSFET device,the threshold voltage decreases drastically.     

Sensitivity of double-gate and FinFETDevices to process variations

We investigate the manufacturability of 20-nm double-gate and FinFET devices in integrated circuits by projecting process tolerances. Two important factors affecting the sensitivity of device electrical parameters to physical variations were quantitatively considered. The quantum effect was computed using the density gradient method and the sensitivity of threshold voltage to random dopant fluctuation was studied by Monte Carlo simulation. Our results show the 3/spl sigma/ value of V/sub T/ variation caused by discrete impurity fluctuation can be greater than 100%. Thus, engineering the work function of gate materials and maintaining a nearly intrinsic channel is more desirable. Based on a design with an intrinsic channel and ideal gate work function, we analyzed the sensitivity of device electrical parameters to several important physical fluctuations such as the variations in gate length, body thickness, and gate dielectric thickness. We found that quantum effects have great impact on the performance of devices. As a result, the device electrical behavior is sensitive to small variations of body thickness. The effect dominates over the effects produced by other physical fluctuations. To achieve a relative variation of electrical parameters comparable to present practice in industry, we face a challenge of fin width control (less than /spl sim/1 nm 3/spl sigma/ value of variation) for the 20-nm FinFET devices. The constraint of the gate length variation is about 10/spl sim/15%. We estimate a tolerance of 1/spl sim/2 /spl Aring/ 3/spl sigma/ value of oxide thickness variation and up to 30% front-back oxide thickness mismatch.     

Polysilicon gate enhancement of the random dopant induced thresholdvoltage fluctuations in sub-100 nm MOSFETs with ultrathin gateoxide

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3D) “atomistic” simulation technique. MOSFETs with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled to thickness in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect of the polysilicon grain boundaries on the threshold voltage variation are also presented     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

Simulation of EPROM programming characteristics

An efficient method for the simulation of EPROM programming based on hydrodynamic calculations of electron energy within the device, is described. After the nonMaxwellian energy distribution is calculated, an expression for injected gate current is integrated to find the total gate charge and hence the threshold voltage shift, as a function of time. Comparison of theoretical and experimental results for actual EPROM programming validates this method.<>     

Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators

This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal–oxide–semiconductor (MOS) device, and demonstrates the threshold voltage shift required in nonvolatile memory devices using a floating gate quantum dot layer. An InGaAs-based nonvolatile memory MOS device was fabricated using a high-κ II–VI tunnel insulator stack and self-assembled GeO _x -cladded Ge quantum dots as the charge storage units. A Si₃N₄ layer was used as the control gate insulator. Capacitance–voltage data showed that, after applying a positive voltage to the gate of a MOS device, charges were being stored in the quantum dots. This was shown by the shift in the flat-band/threshold voltage, simulating the write process of a nonvolatile memory device.     

A self-consistent pseudo-two-dimensional model for hot-electron current in MOST' s

A theoretical formulation for the hot-electron currents (substrate and gate currents) in MOST's with nonuniform impurity profile has been built. By applying a gradual channel approximation for the source section and a pseudo-two-dimensional approximation for the drain section, saturation voltage is obtained by considering the voltage and channel current continuity at the boundary of the two sections. Three fitting parameters in the model are determined by comparing the theoretical calculation results with the observed substrate current in samples with various device parameters. The present model was successfully applied to describe the two experimental results: the gate oxide thickness dependence of the gate current injection efficiency and the kink in the maximum channel electric field strength versus gate voltage (= drain voltage) relation. The nonuniform channel impurity profile is approximated by the modified Gaussian distribution, which is found to agree well with the estimation by the substrate bias effect of MOST's. The calculated gate currents for the device can well explain the implantation energy dependence of the measured gate currents.     

超深亚微米PMOSFET器件的NBTI效应

研究了超深亚微米PMOS器件中的NBTI(负偏置温度不稳定性)效应,通过实验得到了NBTI效应对PMOSFET器件阈值电压漂移的影响,并得到了在NBTI效应下求解器件阈值电压漂移的经验公式.分析了影响NBTI效应的主要因素:器件栅长、硼穿通效应和栅氧氮化以及其对器件寿命退化的作用.给出了如何从工艺上抑制NBTI效应的方法     

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.     

A source-side injection erasable programmable read-only-memory (SI-EPROM) device

A new erasable programmable read-only memory (EPROM) device with promise for low-voltage high-speed programming is described. This device is an asymmetrical n-channel stacked-gate MOSFET, with a short weak gate-control channel region introduced close to the source. At high gate bias, a strong channel electric field is created in this local region even at a relatively low drain voltage. Furthermore, the gate oxide field in this region also aids the injection of hot electrons into the floating gate. As a result, the source-side injection EPROM (SI-EPROM) has shown 10-µs programming speed at a drain voltage of 5 V.