Comparison of drain structures in n-channel MOSFET's

Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.     

Hot-carrier-induced degradation in p-channel LDD MOSFET's

When the p-channel MOSFET is stressed near the maximum substrate current Isub, the lifetime t (5-percent increase in the transconductance) followstI_{sub} = A(I_{sub}/I_{d})^{-n}, with n = 2.0. A simple electron trapping model is proposed to explain the observed power law relationship. The current ratioI_{sub}/I_{d}and the maximum channel electric field decrease with increasing stress time, which is consistent with electron trapping in the oxide during the stress.     

Experimental results on submicron-size p-channel MOSFET's

We report results on p-channel MOSFET's with channel lengths as small as 0.5 µm. Using design criteria obtained from numerical simulation, the devices have been fabricated by a low temperature process with very short annealing times. Fabricated devices with submicron channel lengths are dominated by velocity saturation of holes. Comparing the drive capability of n- and p-channel devices, we find the intrinsic device currents to be within a factor of 1.4 for a channel length of 0.5 µm.     

Hot-carrier drifts in submicrometer p-channel MOSFET's

Hot-carrier-induced shifts in p-channel MOSFET operating characteristics have been observed down to drain voltages of - 6 V. Cases are discussed in which p-MOSFET's show up to two orders of magnitude larger degradation than corresponding n-MOSFET's. The shifts include current and threshold voltage increases. From dependences on stress gate voltage, stress drain voltage, time, and substrate current, the hot-carrier origin of the shifts is specified in detail.     

Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.     

Threshold voltage shift of n-channel Si-gate MOSFET's

The relationship between the threshold voltage shift of the n-channel Si-gate MOSFET and the implant dose of boron ions has been examined theoretically and experimentally when these ions are implanted with an energy of 60 keV through a gate oxide of 1200 Å into a p-type silicon substrate of the acceptor concentration of 7 × 10¹⁴/cm³. The effect of high-temperature treatment after ion implantation on the threshold voltage shift has been considered. The good agreement between the theory and the experiment verifies that the model used is reasonable. The threshold voltage shift with the dose is expressed by about 5 × 10^-12V.cm²below a dose of 5 × 10¹¹ions/cm². Above this value, the increase of the threshold voltage shift becomes slow and the slope takes the value of about 2 × 10^-12V.cm²due to the maximum surface depletion layer.     

Hot-carrier effects in Hydrogen-passivated p-channel polycrystalline-Si MOSFET's

The dependence of hot-carrier effects on channel length and stress-bias voltage in hydrogen-passivated accumulation-mode p-channel polycrystalline-Si MOSFET's operating in the saturation region has been studied, Before stress, these devices exhibit a minimum value of current at VGS≈ 0 V but as VGSincreases above 0 V, they show an increase in (leakage) current due to field-enhanced generation of carriers near the drain. After stress, the current at VGS≈ 0 V increases slightly with respect to its pre-stress value. However, the current then monotonically decreases as VGSincreases above 0 V unlike the situation before stress. No change in reverse mode (source and drain reversed) characteristics and no change in the ON-state (VGS< 0 V) forward-mode characteristic was observed after stress. These observations are shown to be due to hot-carrier-induced acceptor-type interface states near the drain in forward-mode operation.     

Simulating single-event burnout of n-channel power MOSFET's

Single-event burnout of power MOSFETs is a sudden catastrophic failure mechanism that is initiated by the passage of a heavy ion through the device structure. The passage of the heavy ion generates a current filament that locally turns on a parasitic n-p-n transistor inherent to the power MOSFET. Subsequent high currents and high voltage in the device induce second breakdown of the parasitic bipolar transistor and hence meltdown of the device. This paper presents a model that can be used for simulating the burnout mechanism in order to gain insight into the significant device parameters that most influence the single-event burnout susceptibility of n-channel power MOSFETs     

An analytical model for snapback in n-channel SOI MOSFET's

An analytical snapback model for n-channel silicon-on-insulator (SOI) transistors with body either tied to the source or floating is been presented. The snapback is modeled as a nonlinear feedback system leading to negative transconductances from which the jump in current can occur at the point of instability. The crux of this model is based on the strong dependence of the transistor threshold voltage on the body potential when the body potential is above the transistor surface potential at strong inversion. No parasitic bipolar action is invoked to account for the snapback phenomena. The model correctly predicts the occurrence of hysteresis/latch phenomena and the conditions under which the current jump occurs despite some gross approximations in the electric field and the injection level. Results obtained from this model show good agreement with experimental data measured from SIMOX devices fabricated on 0.3-μm epi film     

Effects of hot-carrier trapping in n- and p-channel MOSFET's

Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.     

Comparison between the effects of positive noncatastrophic HBM ESDstress in n-channel and p-channel power MOSFETs

The effect of noncatastrophic positive human body model (HBM) electrostatic discharge (ESD) stress on n-channel power MOSFETs is radically different from that on p-channel MOSFETs. In n-channel transistors, the stress causes negative shifts of the current-voltage characteristics indicative of positive charge trapping in the gate oxide. In p-channel transistors, the stress increases the drain-to-source leakage current, probably due to localized avalanche electron injection from the p-doped drain     

A study of photon emission from n-channel MOSFET's

It is known that an n-channel MOSFET, operating in the saturation region, is accompanied by visible light emission. The spectral distribution of this emitted light is reported in this paper for the first time. It behaves as exp (-α . hv) under various bias conditions (α: constant); the energy state of hot electrons is described as a Maxwell-Boltzmann distribution. The hot-electron temperature in an n-channel MOSFET is experimentally evaluated from the photon spectrum analysis. As compared with the electric field strength calculated by two-dimensional simulation, the hot-electron temperature is found to be determined as a function of the electric field strength in the drain avalanche region.     

Threshold-voltage instability of n-channel MOSFET's under bias-temperature aging

New experimental evidence of positive threshold-voltage shift caused by interface state generation under positive bias-temperature (BT) aging is presented. Interface states were estimated for MOSFET's using low-frequency (8-Hz)C-Vmeasurement, which was carried out by a lock-in technique. Generated acceptor-type interface states are distributed between the midgap and the conduction-band edge in the forbidden gap. Time(t) and temperature(T) dependence for threshold-voltage shift (deltaV_{T}) is represented experimentally asdeltaV_{T}infin log (t/t_{0}), wheret_{0}^{-1} infin exp (-1.0 eV/kT). The positive VTshift appears faster for MOSFET's fabricated with dry O2oxides as gate insulator than for those with HCI oxides. It is also shown that the VTshift is always larger than the flat-band voltage shift caused by interface state generation under negative BT aging. Generated interface states are distributed in the entire forbidden gap, differing from the case of positive BT aging.     

Dual-gate operation and volume inversion in n-channel SOI MOSFET's

The effects of volume inversion in thin-film short-channel SOI MOSFETs and the efficacy of dual-gate operation in enhancing their device performance have been analyzed using two-dimensional device simulations and one-dimensional analytical computations. The analyses have been restricted to the strong inversion regime, which is the practically useful region of operation of the SOI MOSFETs. In this region, the analyses suggest that when compared at constant V _G-V_T values, the dual-channel volume inverted devices do not offer significant current-enhancement advantage, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1-μm range     

Mobility degradation in very thin Oxide p-channel MOSFET's

The effective hole mobility in large-area p-channel MOSFET's decreases systematically over a wide range of oxide fields as the gate oxide thickness decreases from 240 to 31 Å. A scattering mechanism based on the variations of the gate-charge-induced Coulomb scattering potential in the channel resulting from gate oxide thickness and/or structural fluctuations over the gate area is proposed to explain the results.     

Gate current in self-aligned n-channel and p-channel pseudomorphicheterostructure field-effect transistors

A report is presented on the results of the study of the gate leakage current in n-channel and p-channel self-aligned pseudomorphic HIGFETs. The authors demonstrate that in these devices the gate leakage current is practically independent of the gate length. This means that the gate current primarily flows into the source and drain contacts through small sections of the channel near the contacts. At large gate voltages, the gate current is limited by the band discontinuities at the heterointerface, similar to the gate current in non-self-aligned heterostructure field-effect transistors     

Fabrication of inversion-type n-channel MOSFET's using cubic-SiC on Si

Inversion-type n-channel MOSFET's of cubic-SiC were successfully fabricated. Cubic-SiC was grown on Si     

Subquarter-micrometer gate-length p-channel and n-channel MOSFETswith extremely shallow source-drain junctions

The fabrication of p-channel and n-channel MOSFETs with sub-quarter-micrometer n⁺ polysilicon gates, have been fabricated using extremely shallow source-drain (S-D) junctions, is reported p⁺-n junctions as shallow as 80 nm have been fabricated using preamorphization low-energy BF₂ ion implantation and rapid thermal annealing, and 80-nm n⁺-p junctions have been fabricated using low-energy arsenic ion implantation and rapid thermal annealing. n-channel MOSFETs with 80-mm S-D junctions and 0.16-μm gate lengths have been fabricated, and a maximum transconductance of 400 mS/mm has been obtained. 51-stage n-channel enhancement-mode/enhancement-mode (E/E) ring oscillators and p-channel E/E ring oscillators with extremely shallow S-D junctions have also been obtained