Characteristics of field-induced-drain (FID) poly-Si TFTs with highon/off current ratio

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with a field-induction-drain (FID) structure using an inversion layer as a drain are investigated. The FID structure not only reduces the anomalous leakage current, but also maintains a high on current. An off current of 1.5 pA/μm and an on/off current ratio of 10⁷ (V_d=10, V_g =-20 V) are successfully obtained. These characteristics result from good junction characteristics between the p channel and n⁺ inversion layer. Reducing the threshold voltage of the FID region allows a simple circuit configuration for the FID TFTs     

Anomalous variations of OFF-State leakage current in poly-Si TFTunder static stress

Studies the anomalous variations of the OFF-state leakage current (I_OFF) in n-channel poly-Si thin-film transistors (TFTs) under static stress. The dominant mechanisms for the anomalous I_OFF can be attributed to (1) I_OFF increases due to channel hot electrons trapping at the gate oxide/channel interface and silicon grain boundaries and (2) I_OFF decreases due to hot holes accumulated/trapped near the channel/bottom oxide interface near the source region. Under the stress of high drain bias, serious impact ionization effect will occur to generate hot electrons and hot holes near the drain region. Some of holes will be injected into the gate oxide due to the vertical field (~(V_Gstress V_Dstress)/T _OX) near the drain and the others will be migrated from drain to source along the channel due to lateral electric field (~V_Dstress/L_CH)     

Hot-carrier effects and reliable lifetime prediction in deepsubmicron N- and P-channel SOI MOSFETs

Hot-carrier effects are thoroughly investigated in deep submicron N- and P-channel SOI MOSFETs, for gate lengths ranging from 0.4 μm down to 0.1 μm. The hot-carrier-induced device degradations are analyzed using systematic stress experiments with three main types of hot-carrier injections-maximum gate current (V_g≈V_d ), maximum substrate current (V_g≈V_d/2) and parasitic bipolar transistor (PBT) action (V_g≈0). A two-stage hot-carrier degradation is clearly observed for all the biasing conditions, for both N- and P-channel devices and for all the gate lengths. A quasi-identical threshold value between the power time dependence and the logarithmic time dependence is also highlighted for all the stress drain biases for a given channel length. These new findings allow us to propose a reliable method for lifetime prediction using accurate time dependence of degradation in a wide gate length range     

On the drain current saturation in short channel MOSFETs

Submicron MOSFETs are the issue for ULSI integrated circuits. However, drastic reduction of device size leads to a complex modeling of the MOSFET drain current, which is affected by the electrical and physical phenomena induced by the low device dimension. Several current models are proposed to explain the drain current behavior in the saturation region of the I_D-V_D characteristic curve. Mainly, we can distinguish two types: long channel and short channel current modeling. In the present work, a survey of current voltage models is presented aiming a contribution to the interpretation of the current behavior in the saturation region of the I-V curves, i.e. non-saturation of the drain current, which are critical in submicronic devices.     

On the geometric component of charge-pumping current in MOSFETs

A simple method of unambiguously determining the presence of any geometric component in a charge-pumping measurement by collecting this component at another node via a nearby junction is presented. With the method it has been possible to study the dependence of geometric components on device dimensions and various experimental conditions with unprecedented sensitivity. By effectively separating the two current contributions, this method can at the same time be used to reduce geometric components in the regular charge-pumping signal, thereby increasing the accuracy of the various implementations of the charge pumping (CP) technique     

On the channel-length dependence of the hot-carrier degradation ofn-channel MOSFETs

The channel-length dependence of lifetime plots is analyzed. It is shown that no unique τ*I_d versus I_sub/I_d relation can be obtained when threshold-voltage shifts are used for measuring the lifetime. In contrast, when using charge pumping as a monitor for the degradation, the lifetime plot for a given technology proves to be independent of the channel length     

The effect of Fowler-Nordheim tunneling current stress on mobilityin n-channel MOSFETs

The electron effective mobility in n-channel MOSFETs has been investigated under Fowler-Nordheim (F-N) tunneling current stress at room temperature. With F-N current stress, mobilities become smaller than of the prestress mobilities over the whole region of inversion carrier density N_inv, and the N_inv -dependence of the mobility almost disappears     

Hot-carrier stress effects on gate-induced-drain leakage current in n-channel MOSFETs studied by hydrogen/deuterium isotope effect

The degradation of gate-induced-drain leakage (GIDL) current under hot-carrier stress (HCS) has been studied in n-channel MOSFETs that were annealed in hydrogen (H) or deuterium (D). It is found that the degradation of GIDL current (I/sub GIDL/) can be effectively suppressed by deuterium passivation of interface traps. By using the H/D isotope effect, the impacts of oxide charge trapping (/spl Delta/N/sub ox/) and interface trap generation (/spl Delta/N/sub it/) on I/sub GIDL/ are successfully separated. The results indicate that, depending on stress and measurement conditions, I/sub GIDL/ may increase or decrease under HCS. /spl Delta/N/sub ox/ alters I/sub GIDL/ at high electric fields by varying the band-to-band tunneling current. /spl Delta/N/sub it/ alters I/sub GIDL/ at a low electric field by introducing a trap-assisted leakage component. Furthermore, evidence of hole trapping at the peak substrate current stress is indisputably presented for the first time and its impact on I/sub GIDL/ is discussed.     

A thorough investigation of hot-carrier-induced gate oxide breakdown in partially depleted N- and P-channel SIMOX MOSFETs

In this paper, the hot-carrier-injected oxide region in the front interfaces is systematically investigated for partially depleted silicon-on-insulator (PDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) devices fabricated on a SIMOX wafer. The gate oxide properties associated with channel hot-carrier effects are investigated and the hot-carrier-induced device degradations are analyzed using stress experiments with three main types of hot-carrier injections-maximum gate current, maximum substrate current and parasitic bipolar transistor action. Based on experimental results, the influence of these injected carriers on the gate oxide properties is clarified. As a matter of fact, NMOSFETs degradation mechanism is shown to be caused by hot holes injected into the drain side of the gate oxide, and electrons trapped in the gate oxide can accelerate the gate oxide breakdown. PMOSFETs degradation mechanism depends on the biasing conditions. For the first time, we conclude that the electrical characteristics of NMOSFETs are significantly different from that of PMOSFETs after the gate oxide breakdown. An extensive discussion of the experimental results is provided.     

Identification of electron trap location degrading low-frequency noise and PBTI in poly-Si/HfO2/interface-layer gate-stack MOSFETs

Identification of electron trap location in HfO₂/interface-layer (IFL) of poly-Si/TiN/HfO₂/SiO₂ gate-stacked MOSFETs is successfully demonstrated through analysis of low-frequency noise and PBTI characteristics with respect to nitrogen incorporation into the gate dielectrics in fabrication process. It is found that the electron trap existing in the bulk-IFL dominantly degrades low-frequency noise (LFN) and positive bias temperature instability (PBTI). The pre-existing electron trap is considered to be generated by N incorporation into the IFL in the fabrication process of gate-first process.     

Thermally generated leakage current mechanisms of metal-induced laterally crystallized n-type poly-Si TFTs under hot-carrier stress

Mechanisms of thermally generated leakage current have been systematically studied for metal-induced laterally crystallized n-type polycrystalline silicon thin film transistors under the hot-carrier stress. Various mechanisms of thermally generated leakage current are identified by both forward and reverse modes. The decrease of thermally generated leakage current is attributed to the depletion region modulation effect, which results from its shrinkage. While the increase of thermally generated leakage current is caused by the increase of the donor trap density, its increment relative to the initial one follows the Schottky model in the forward mode. Overall, the depletion region modulation effect dominates and the thermally generated leakage current decreases.     

On the tunneling component of charge pumping current in ultrathingate oxide MOSFETs

A simple method is described for separating the charge pumping current from the parasitic tunneling component in a charge pumping measurement performed on MOS transistors with ultrathin (<2 nm) gate oxide thickness. The method is presented here for a two-level charge pumping signal and can be used to significantly increase the accuracy of the technique to extract interface trap parameters in tunnel MOS devices     

Novel SiC/Si heterostructure negative-differential-resistance diodefor use as switch with high on/off current ratio and low powerdissipation

A novel p-SiC/n-Si heterostructure negative-differential-resistance (NDR) diode with special current-voltage (I-V) characteristics is reported. Under reverse biases, the I-V curve of this device possesses an N-shaped NDR with a high peak-to-valley current ratio (PVCR) and a broad high-impedance valley region. For use as a switch, it can easily achieve a very low off-state current and a high on/off current ratio, as compared to the conventional N-shaped NDR devices. Hence, performance with a more effective switching action and lower power dissipation can be expected. Furthermore, obvious NDR's can even be obtained at a temperature up to 300°C, indicating this device is also potential for high-temperature applications     

Tunneling leakage current in oxynitride: dependence onoxygen/nitrogen content

It is widely known that the addition of nitrogen in silicon oxide, or the addition of oxygen in silicon nitride, affects its reliability as a gate dielectric. The authors examine the gate leakage current as a function of the oxygen and nitrogen contents in ultrathin silicon oxynitride films on Si substrates. It is shown that, provided that electron tunneling is the dominant current conduction mechanism, the gate leakage current in the direct tunneling regime increases monotonically with the oxygen content for a given equivalent oxide thickness (EOT), such that pure silicon nitride passes the least amount of current while pure silicon oxide is the leakiest     

Temperature dependence of drain-induced barrier lowering in deepsubmicrometre MOSFETs

A new method for extracting the drain-induced barrier lowering (DIBL) parameter in an MOS transistor is proposed. This method is used to study the influence of temperature on the DIBL effect. It is found that the DIBL parameter is almost independent of temperature between 50 and 300 K. This method makes it also possible to recalculate the intrinsic output characteristics that the device would have in the absence of DIBL, and, in turn, to evaluate the intrinsic device saturation parameters     

Enhanced gate induced drain leakage current in HfO2 MOSFETs

The substrate current of high-κ dielectric MOSFETs has been studied using dc sweep and transient (down to 100 μs per I-V curve) electrical measurements. These measurements reveal trap-assisted substrate current components in addition to the traditional bell-shaped impact ionization current. By separating the transversal and lateral electric field contributions, the gate induced drain leakage (GIDL) is shown to dominate the substrate current at low gate biases. At high gate biases, tunneling of valence band electrons from the bulk to the gate dominates. The results show that the GIDL current is the result of band-to-band tunneling assisted by traps located at the HfO₂/SiO₂ interface and transition layer, and not the result of oxide charging.     

On the current dependence of low-frequency noise in bipolar transistors

The bias dependent characteristics of the base input flicker noise or 1/f noise current generator in bipolar transistors is examined. A simple technique is presented for the determination of the flicker noise magnitude at selected low frequencies with varying collector bias current. The results indicate that the bias dependence of the flicker noise is intimately rated to that of the input conductance parameter gπin the common-emitter configuration. Practical methods are given for the determination of the bias-independent noise parameter ρ0, which, in conjunction with the small-signal network parameters, fully characterize the device noise performance at low frequencies, ρ0, is an equivalent noise resistance representing the open-circuit flicker noise voltage at the base terminal at 1 Hz. Results of noise figure measurements on several representative commercially available devices are compared with those calculated with a knowledge of ρ0.     

Noise model of gate-leakage current in ultrathin oxide MOSFETs

A physics-based analytical model of the gate-leakage current noise in ultrathin gate oxide MOSFETs is presented. The noise model is based on an inelastic trap-assisted tunneling transport. We employ the barrier height fluctuation model and the Lorentzian-modulated shot noise of the gate-leakage current stemming from the two-dimensional electron gas channel to explain the excess noise behavior. The excess noise can be interpreted as the sum of 1/f/sup /spl gamma// noise and the Lorentzian-modulated shot noise. Trap-related processes are the most likely cause of excess current noise because slow traps in the oxide can result in low-frequency dissipation in the conductance of oxides and fast traps can produce the Lorentzian-modulated shot noise associated with generation-recombination process at higher frequencies. In order to verify the proposed noise model, the simulation results are compared with experimental data, and excellent agreement is observed.     

On interface and oxide degradation in VLSI MOSFETs. II.Fowler-Nordheim stress regime

For pt. I see ibid., vol. 49, pp. 247-53 (2002).The assessment of the physical mechanisms governing the degradation of thin oxides is a very important and, unfortunately, elusive issue that has raised significant debate in recent literature. In this paper, we first use some of the results reported in Pt. I to estimate a reasonable boundary for the efficiency of a possible hydrogen release (HR) mechanism and argue that the HR appears too weak to explain our measurements of stress-induced leakage current (SILC) produced by Fowler-Nordheim (FN) tunneling stress measurements. Then, we present an in-depth investigation of the anode hole injection (AHI) mechanism at low stress gate voltages (V_G). To this purpose, we used both previously discussed and ad hoc devised characterization techniques. Our results indicate that AHI is still operative at V_G lower than previously experimentally demonstrated. Furthermore, the correlation between the energy of holes at the anode, their injection into the oxide, and the eventual generation of SILC strongly indicate that AHI is the mechanism governing oxide degradation in the considered stress conditions     

Extraction of trap densities in entire bandgap of poly-Si thin-film transistors fabricated by solid-phase crystallization and dependence on process conditions of post annealing

Trap densities (D_t) in entire bandgaps of poly-Si thin-film transistors (TFTs) fabricated by solid-phase crystallization (SPC) have been extracted by measuring low-frequency capacitance-voltage characteristics and using an extraction algorithm. The extraction algorithm is explained in detail. D_t in the upper and lower halves of the bandgap is extracted from n- and p-type TFTs, respectively. It is found that D_t is very roughly 10¹⁸ cm⁻³ eV⁻¹ near the midgap and becomes tail states near the conduction and valence bands. As a result, D_t is distributed like U shape in the bandgap, but humps appear around the midgap. Moreover, the dependence of D_t on process conditions of post annealing has been evaluated. It is found that the hump can be reduced by increasing annealing temperature and time because crystal defects generated during the SPC are extinguished during the post annealing.