Low power 13 Gbit/s VCSEL current driver in 0.18 μm CMOS for optical interconnection

A design of 13 Gbit/s vertical cavity surface emitting laser (VCSEL) driver using 0.18 μm complementary metal oxide semiconductor (CMOS) technology is presented in this paper. The core unit of the driver consists of pre-amplify stage and output stage circuit. Techniques of three stages differential amplifier with low impedance load and active feedback are employed in pre-amplify stage, and technique of C3A is adopted in output stage to acquire low power consumption and high speed. The experimental results show that the circuit can work at the data rate of 10 Gbit/s and maximum of 13.2 Gbit/s. The output modulation current is up to 12.5 mA and the power dissipation is only 68 mW with a 1.8 V power supply.     

40 Gbit/s monolithic integrated modulator driver in InP SHBT technology

A high-speed and high-gain modulator driver circuit is presented using 4-inch InP SHBT technology. The IC was developed for driving EAM modulators in 40 Gbit/s optical fibre systems. The monolithic integrated circuit features output amplitude control and output crossing point control. Measured results show the circuit operates at 40 Gbit/s with a swing of 2.5 V/sub p-p/ at each output and 9/8 ps rise/fall times. The power dissipation is 1.5 W with a standard power supply of -5.2 V.     

基于差分编码技术的12.5 Gbit/s高速SerDes发射机

研究并设计了一种基于差分编码技术的12.5 Gbit/s高速SerDes发射机.该电路由并串转换模块、去加重控制模块和驱动模块组成.驱动模块采用电流模逻辑异或门结构,动态负载的加入可以在降低功耗的同时实现与传输线的阻抗匹配.首次提出在并串转换模块中加入差分编码电路的解决方案,以保证原码输出,从而使数据在发射机内完成差分...     

Monolithic 2.1 Gbit/s decision circuit with a decision threshold ambiguity width of less than 10 mV

An Si bipolar monolithic decision circuit for practical use is developed using an improved circuit technique and super self-aligned process technology with the reliable 1.25 ?m rule. The circuit consists of a slice amplifier, a master-slave D flip-flop and an output buffer. This circuit is capable of operating up to 2.1 Gbit/s with a decision threshold ambiguity width of less than 10 mV. In addition, a clock phase margin of 250 degrees and power dissipation of 640 mW at VEE=?6 V can be achieved.     

40 Gbit/s lumped-element modulator driver in GaAs pHEMTs

A high-speed and high-gain modulator driver circuit using 0.15 /spl mu/m gate length GaAs pHEMT technology is presented. The IC was developed for driving electroabsorption modulators in 40 Gbit/s optical fibre systems. To meet application requirements a lumped-element approach was used with differential configuration. Measured results show the circuit operates at 40 Gbit/s with a swing of 3 V/sub p-p/ for single-ended and 6 V/sub p-p/ for differential output, and 8/10 ps rise/fall times.     

Comparison of InP/InGaAs DHBT distributed amplifiers as modulator drivers for 80-Gbit/s operation

This paper compares three single-ended distributed amplifiers (DAs) realized in an in-house InP/InGaAs double heterojunction bipolar transistor technology featuring an f/sub t/ and f/sub max/ larger than 200 GHz. The amplifiers use five or eight gain cells with cascode configuration and emitter follower buffering. Although the technology is optimized for mixed-signal circuits for 80 Gbit/s and beyond, DA results could be achieved that demonstrate the suitability of this process for the realization of modulator drivers. The results are documented with scattering parameter, eye diagram, and power measurements. This includes amplifiers featuring a 3-dB bandwidth exceeding 80 GHz and a gain of over 10 dB. One of the amplifiers exhibits clear eyes at 80 Gbit/s with a gain of 14.5 dB and a voltage output swing of 2.4 V/sub pp/ limited by the available digital input signal. This amplifier delivers an output power of 18 dBm (5.1 V/sub pp/) at 40 GHz and 1-dB compression. Two amplifiers offer a tunable gain peaking, which can be used to optimize circuit performance and to compensate losses in the circuit environment. The results show that, using our InP/InGaAs technology, an integration of high-speed mixed-signal circuits (e.g., multiplexers) and high-power modulator drivers on a single chip is feasible.     

Diode multiplexer in the multi-Gbit/s range

A clocked multiplexer circuit was realised which provided 4.48 Gbit/s, 5 Gbit/s, and 7.84 Gbit/s output-pulse streams for p.c.m.-type input tributaries at 1.12 Gbit/s, 0.25 Gbit/s, and 1.12 Gbit/s, respectively. The circuit employed essentially ultra-broadband 180° hybrids, step-recovery diodes, and GaAs Schottky-barrier diodes. Output voltages up to 2 V were obtained across a load of 50 ?. The pulse width of the output pulses was approximately 100 ps.     

用于SDH STM-64光接收机的GaAs HBT限幅放大器

采用2μm GaAs HBT工艺实现了10Gb/s的限幅放大器.整个系统包括一级输入缓冲、三级放大、一级用于驱动50Ω传输线的输出缓冲和失调电压补偿回路四个部分.采用双电源供电,正电源为3.3V,负电源为-2V,功耗为500mW.在输出电压幅度保持恒定(单端峰峰值300mV)的条件下,输入动态范围约为38dB.芯片面积为1.15×0.7mm².     

10-13.6 Gbit/s 0.18 /spl mu/m CMOS modulator drivers with 8 V/sub PP/ differential output swing

A novel intrinsic drain-gate capacitance (C/sub DG/) feedback network is incorporated into the conventional cascode circuit configuration to implement a 10-13.6 Gbit/s modulator driver. The driver fabricated in 0.18 /spl mu/m CMOS process could generate an 8 V/sub PP/ differential output swing. The power consumption is as low as 0.6 W. The present work shows that the driving capability is greater than the currently reported CMOS drivers.     

5 V, 10 Gbit/s optical receiver module using Si-bipolar IC

A 10 Gbit/s optical receiver module using a Si-bipolar IC has been developed. For low power and low cost, a pure Si-bipolar IC is used in place of a GaAs IC, which is commonly used for over 10 Gbit/s. To widen the frequency bandwidth, multifeedback techniques and a two-stage buffer configuration are used in the preamplifier IC. In addition, a differential circuit configuration is used for stable operation at high frequency. The IC was fabricated using 0.25 μm Si-bipolar technology. The module exhibits sensitivity of <-16 dBm for 10 Gbit/s data with an input dynamic range >15 dB. Small power consumption of 410 mW is achieved with the single power-supply voltage of +5 V     

Low-power 50 Gbit/s InP HBT 1:4 demultiplexer IC with multiphase clock architecture

An InP HBT 1:4 demultiplexer IC with a multiphase clock architecture is described that reduces the number of circuit elements and power consumption while maintaining operating speed. The IC operated at 50 Gbit/s with 1.17 W power consumption at a supply voltage of -4.5 V. Compared to an IC with a conventional tree-type architecture using the same InP HBTs, the power consumption is less than half while the operating speed of 50 Gbit/s is maintained.     

Scalable 10 Gbit/s 4×20.25 μm CMOS/SIMOX ATM switch LSIcircuit based on distributed contention control

A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput, 0.2 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption     

超高速单电源GaAs判决再生电路

设计并模拟分析了光纤通信用超高速单电源 Ga As判决再生电路 ,采用非掺 SI Ga As衬底直接离子注入、1μm耗尽型 Ga As MESFET、平面电路工艺研制出单片 Ga As判决再生电路。实验测试结果表明 ,该电路可对输入信号进行正确的“0”、“1”判决 ,并经时钟抽样后 ,输出正确的数字信号 ,传输速率可达 2 .8Gbit/s,可用于覆盖 2 .5Gbit/s系列光通信系统     

ESD protection for 10 Gbit/s optical receivers

The ESD protection of high-speed RF ICs used in 10 Gbit/s optical receivers with InGaP heterojunction bipolar transistor (HBT) technology is presented. The frequency response of a 10 Gbit/s optical receiver with ESD protection is directly measured. The results indicate that the new ESD circuit can effectively protect input/output pins while with negligible loading effect.     

1.25 Gbit/s光接收机限幅放大器

文章介绍了采用0.35 μm双极型互补氧化物半导体(BiCMOS)工艺制作的光纤通信用低功耗的1.25 Gbit/s限幅放大器,其电路采用3.3 V单电源供电,电路增益可以达到70 dB,功耗为20 mW,在27 dB的输入动态范围内,可以保持800 mV的恒定输出摆幅.整个芯片的面积为1.30 mm×0.75 mm.     

基于130 nm CMOS工艺的5 Gbit/s 10:1并串转换芯片

介绍了一种基于GSMC 130 nm CMOS工艺的高速率低功耗10:1并串转换芯片。在核心并串转换部分,该芯片使用了多相结构和树型结构相结合的方式,在输入半速率时钟的条件下,实现了10路500 Mbit/s并行数据到1路5 Gbit/s串行数据的转换。全芯片完整后仿真结果显示,在工作电压(1.2±10%)V、温度-55~100℃、全工艺角条件下,该芯片均可正确完成10:1并串转换逻辑功能,并输出清晰干净的5 Gbit/s眼图。在典型条件下,芯片整体功耗为25.2 mW,输出电压摆幅可达到260 mV。     

10Gb/s NRZ码时钟信息提取电路

利用法国OMM IC公司的0.2μm G aA s PHEM T工艺,设计实现了10 G b/s NRZ码时钟信息提取电路。该电路采用改进型双平衡G ilbert单元的结构,引进了容性源极耦合差动电流放大器和调谐负载电路,大大提高了电路的性能。测试表明:在输入速率为9.953 28 G b/s长度为223-1伪随机序列的情况下,提取出的时钟的均方根抖动是1.18 ps,峰峰值抖动是8.44 ps。芯片面积为0.5 mm×1 mm,采用-5 V电源供电,功耗约为100 mW。     

A bipolar monolithic multigigabit/s decision circuit

A monolithic multigigabit/s decision circuit using a 0.5-/spl mu/m bipolar process technology called advanced super self-aligned technology (SST-1A) has been developed. A special decision circuit including a novel current switch based on a nonthreshold logic circuit and a cutoff prevention principle was designed and fabricated. An output voltage swing of 1 V across a 50-/spl Omega/ load, a fast transition time of 90 ps (10-90%) and 3.6 Gbit/s operation have been achieved. Power dissipation per chip is about 600 mW. This IC is applicable to very-high-speed optical fiber transmission system repeaters.     

Wideband fully differential CMOS transimpedance preamplifier

A fully differential transimpedance amplifier has been designed and implemented in 0.18 /spl mu/m standard digital CMOS technology. The parallel feedback circuit topology is adopted to broaden the bandwidth. It can operate at 10 Gbit/s with the dynamic range from 25 /spl mu/A up to 2.5 mA. The power consumption is only 88 mW under 2 V supply voltage.     

Ultrahigh-speed driverless MQW intensity modulator, and 20 Gbit/s, 100 km transmission experiments

An InGaArInAlAs MQW modulator with the low voltage of 1.5 V for 10 dB extinction ratio and 16 GHz bandwidth has been developed. This ultrahigh-speed modulator enables the modulator driver to be eliminated from the transmitter. 100 km transmission experiments have been carried out using either a 1 V peak to peak output monolithic-IC-driven modulator at 15 Gbit/s or a 2 V peak to peak output multiplexer-driven modulator at 20 Gbit/s. This is the first report on multigigabit operation of MQW modulators to the authors' knowledge.<>