基于振荡器的真随机数发生器的研究

以基于振荡器的真随机数发生器为研究对象,理论分析了影响随机数发生器输出随机性的关键因素.对影响随机性的因素给出不同的参数选取,并使用Matlab软件对各种条件下输出序列的0/1概率差进行了计算,分别验证了采样时刻、高频占空比等因素对真随机数发生器输出的影响,给出了能够提高基于振荡器采样的真随机数发生器随机性的具体方法.所得的结论对设计一个具体的基于振荡器的真随机数发生器具有明确的指导意义.     

利用竞争冒险的真随机数发生器设计

针对真随机数广泛应用的现状,基于振荡器采样和反馈电路竞争冒险机制,分析和设计了一款真随机数发生器。采用VHDL语言为描述工具,以纯数字IP核的形式提供了该发生器,并给出了一种与微控制器OC8051 IP核的挂接方法。选用Ahera Cyclone—Ⅱ FPGA开发板对随机数发生器进行验证,结果表明其逻辑和时序工作稳定,且随机数产生速率可达7．85M／s,完全通过7种随机性检测,可应用于实际的工程开发中。     

应用于UHF RFID标签的低功耗真随机数发生器

设计了一种基于振荡采样法的真随机数发生器.针对UHF RFID标签芯片功耗低、面积小的特点,利用简单有效的电路结构增强发生器的随机性.采用频率受控的被采样数据振荡器与采样时钟异或后形成初步随机数,并增加异或链输出负反馈结构,有效提高了输出序列中"0""1"分布的均匀性,降低了序列的自相关性.标签采用SMIC 0.18μm RF CMOS工艺设计并流片,采样时钟为2MHz,总工作电流少于2μA.     

一种无记忆的真随机数发生器

基于传统的振荡采样电路,设计了一种无记忆的真随机数发生器,从理论上保证了输出是相互独立的.采用弹性函数作为后处理,以较小的硬件代价改善了随机数的统计性能.用纯数字电路在FPGA平台上实现,并验证了该真随机数发生器的性能.测试结果表明该真随机数发生器具有较高的数据输出率和良好的统计特性,适合应用于密码系统中.     

一种高速低功耗真随机数发生器

提出了一种基于环形振荡器采样结构的高速低功耗真随机数发生器(TRNG).其随机性源自环形振荡器的抖动,4个长度互为质数的振荡器链构成了熵源.对振荡器的输出进行异或运算,提高了随机特性,并从数学上予以证明.输出序列经冯诺依曼矫正器进行纠偏,可完全消除比特位间的偏置性.设计了一种精巧的扩散函数,对输出序列做映射处理,进一步提高了其随机特性和分布特性.测试结果表明,TRNG输出比特流通过了Diehard和NIST SP 800-22的系列测试,比特率达20Mb/s.采用0.18μm CMOS工艺设计实现,面积为0.0135mm2,3.3V供电时功耗仅为0.75mW,适合在高速片上加密系统中应用.     

一种基于亚稳态的真随机数发生器

设计实现了一种64位输出的真随机数发生器。在传统Fibonacci环形振荡器和Galois环形振荡器的基础上,通过控制电路使环形振荡器的输出在亚稳态与稳态之间不断切换,为生成的随机序列引入真随机性。通过加入后处理模块,提高随机序列的质量和增加每比特的熵,并利用DES算法实现随机序列的重新组合。利用FPGA进行实验验证后,最终集成在一个加密USB盘控制器芯片内,产生的随机序列通过了NIST SP800-22标准检测。采用110 nm CMOS工艺,该芯片实现了批量生产。     

一种基于FPGA的Latch结构真随机数发生器

提出一种基于FPGA的高熵真随机数发生器,采用非传统锁存器结构,并结合改进的随机数采集方法来获取真随机数。相对于FPGA上广泛采用的真随机数发生器,该高熵真随机数发生器具有较低的资源消耗。与参考方法相比,改进的随机数采集方法有效提升了数据产生速率。实验结果表明,该真随机数发生器对于温度(20 ℃~80 ℃)和电压(0.9~1.1 V)的变化具有较高的鲁棒性,所产生的真随机数均能通过NIST随机性测试。在正常工作条件下,随机数产生速率为14.2 Mbit/s。     

一种基于单电子隧穿结和MOS晶体管的混合随机数发生器

提出了一种新颖的单电子随机数发生器(RNG).该随机数发生器由多个单电子隧穿结(MTJ)以及单电子晶体管(SET)/MOS管混合输出电路组成.MTJ被用于实现一个高频率的振荡器.它利用了电子隧穿的物理随机性得到了很大的振荡频率漂移.SET/MOS管输出电路放大并输出MTJ振荡器的输出信号.该信号经过一个低频信号采样后,产生随机数序列.所提出的随机数发生器使用简单的电路结构产生了高质量的随机数序列.它具有简单的结构,输出随机数的速度可以高达1GHz.同时,该电路还具有带负载能力以及很低的功耗.这种新颖的随机数发生器对未来的密码和通讯系统具有一定的应用前景.     

一种基于单电子隧穿结和MOS晶体管的混合随机数发生器

提出了一种新颖的单电子随机数发生器(RNG).该随机数发生器由多个单电子隧穿结(MTJ)以及单电子晶体管(SET)/MOS管混合输出电路组成.MTJ被用于实现一个高频率的振荡器.它利用了电子隧穿的物理随机性得到了很大的振荡频率漂移.SET/MOS管输出电路放大并输出MTJ振荡器的输出信号.该信号经过一个低频信号采样后,产生随机数序列.所提出的随机数发生器使用简单的电路结构产生了高质量的随机数序列.它具有简单的结构,输出随机数的速度可以高达1GHz.同时,该电路还具有带负载能力以及很低的功耗.这种新颖的随机数发生器对未来的密码和通讯系统具有一定的应用前景.     

一种基于FPGA实现的真随机数发生器

本文分析和实现了一种基于FPGA的真随机数发生器,采用对延迟链各级输出同时采样的方法来增加输出序列的随机性。电路为纯数字形式,50MHz采样时钟采得的输出数据可以无需后处理,直接通过随机性测试,且未发现随机性与采样频率存在显著联系。     

一种基于FPGA的真随机数发生器设计与实现

设计并实现了一种基于FPGA的真随机数发生器,利用一对振荡环路之间的相位漂移和抖动以及亚稳态作为随机源,使用线性反馈移位寄存器的输出与原始序列运算作为后续处理。在Xilinx Virtex-5平台的测试实验中,探讨了振荡器数量以及采样频率等参数对随机序列的统计特性的影响。测试结果表明本设计产生的随机序列能够通过DIEHARD测试,性能满足要求。由于仅使用了普通逻辑单元,使得本设计能够迅速移植到ASIC设计,大大缩短了开发周期。     

Ultra-Low Power Truly Random Number Generator for RFID Tag

This paper proposes low power, low voltage Truly Random Number Generators (TRNG) for Electrical Product Code (EPC Generation 2 Radio Frequency Identification (RFID) tag. Design considerations and trade-offs among randomicity, chip area and power consumption are analyzed according to the special requirements of Gen2 RFID tag. The proposed TRNG circuits consist of an analog random seed generator which uses the oscillator sampling mechanism, and Linear Feedback Shift Registers for post digital processing. These TRNG are implemented in SMIC 0.18 μm CMOS process. And their randomicity performances are verified by the FIPS 140-2 standard for security. One of the TRNG circuits outputs a random bit series at a speed of 40 kHz. Its power consumption is 1.04 μW and chip area is 0.05 mm². The other one has a bit rate at 48 kHz. It has a power consumption of 2.6 μW and chip area of 0.018 mm². The features of low power and small chip area in these TRNG circuits provide a good choice to solve the security and privacy problems in RFID systems.     

On the Security of Oscillator-Based Random Number Generators

Physical random number generators (a.k.a. TRNGs) appear to be critical components of many cryptographic systems. Yet, such building blocks are still too seldom provided with a formal assessment of security, in comparison to what is achieved for conventional cryptography. In this work, we present a comprehensive statistical study of TRNGs based on the sampling of an oscillator subject to phase noise (a.k.a. phase jitters). This classical layout, typically instantiated with a ring oscillator, provides a simple and attractive way to implement a TRNG on a chip. Our mathematical study allows one to evaluate and control the main security parameters of such a random source, including its entropy rate and the biases of certain bit patterns, provided that a small number of physical parameters of the oscillator are known. In order to evaluate these parameters in a secure way, we also provide an experimental method for filtering out the global perturbations affecting a chip and possibly visible to an attacker. Finally, from our mathematical model, we deduce specific statistical tests applicable to the bitstream of a TRNG. In particular, in the case of an insecure configuration, we show how to recover the parameters of the underlying oscillator.     

Linear Corrector Overcoming Minimum Distance Limitation for Secure TRNG from (17, 9, 5) Quadratic Residue Code

A true random number generator (TRNG) is widely used to generate secure random numbers for encryption, digital signatures, authentication, and so on in crypto‐systems. Since TRNG is vulnerable to environmental changes, a deterministic function is normally used to reduce bias and improve the statistical properties of the TRNG output. In this paper, we propose a linear corrector for secure TRNG. The performance of a linear corrector is bounded by the minimum distance of the corresponding linear error correcting code. However, we show that it is possible to construct a linear corrector overcoming the minimum distance limitation. The proposed linear corrector shows better performance in terms of removing bias in that it can enlarge the acceptable bias range of the raw TRNG output. Moreover, it is possible to efficiently implement this linear corrector using only XOR gates, which must have a suitable hardware size for embedded security systems.     

Truly random number generators based on a non-autonomous chaotic oscillator

A non-autonomous chaotic circuit which is suitable for high-frequency integrated circuit (IC) realization is presented. Simulation and experimental results verifying the feasibility of the circuit are given. We have numerically verified that the bit streams obtained from the stroboscopic Poincaré map of the system passed the four basic tests of FIPS-140-2 test suite. We also have verified that the binary data obtained from the hardware realization of this continuous-time chaotic oscillator in the same way pass the full NIST random number test suite. Then, in order to increase the output throughput and the statistical quality of the generated bit sequences, we propose a TRNG design which uses a dual oscillator architecture with the proposed continuous-time chaotic oscillator. Finally, we have experimentally verified that the binary data obtained by this oscillator sampling technique pass the tests of full NIST random number test suite without Von Neumann processing for a higher throughput speed while compared with the previous one where the proposed continuous-time chaotic oscillator is used alone.     

基于压控振荡器的真随机数发生器设计

通过对频率抖动机理的研究,提出一种基于压控振荡器（Voltage-Controlled Oscillator,VCO）的真随机数发生器（True Random Number Generator,TRNG）设计方案.该方案将电阻热噪声放大后作为VCO的控制信号使其振荡频率在中心频率附近随机抖动.VCO所产生的慢振荡信号对周期固定的快振荡信号采样生成原始随机序列,然后利用后处理电路提高序列均匀性并消除自相关性.通过热噪声发生器调节VCO的中心频率可实现序列比特率和随机性之间的权衡.所提电路采用SMIC 55nm CMOS工艺设计,芯片面积0.0124mm²,比特率10Mbps,平均功率0.81mW.输出的随机序列通过NIST SP 800-22测试.     

High speed true random number generator with a new structure of coarse-tuning PDL in FPGA

A metastability-based TRNG (true random number generator) is presented in this paper,and implemented in FPGA.The metastable state of a D flip-flop is tunable through a two-stage PDL (programmable delay line).With the proposed coarse-tuning PDL structure,the TRNG core does not require extra placement and routing to ensure its entropy.Furthermore,the core needs fewer stages of coarse-tuning PDL at higher operating frequency,and thus saves more resources in FPGA.The designed TRNG achieves 25 Mbps@100 MHz throughput after proper post-processing,which is several times higher than other previous TRNGs based on FPGA.Moreover,the robustness of the system is enhanced with the adoption of a feedback system.The quality of the designed TRNG is verified by NIST (National Institute of Standards and Technology) and also accepted by class P 1 of the AIS-20/31 test suite.     

一种基于混沌的鲁棒低功耗真随机数发生器

提出了一种低功耗真随机数发生器,它基于简单的伯努利移位混沌映射,并通过对映射进行特殊扩展来保证在实际实现中保持鲁棒性.映射由开关电流技术实现,从而使其可以完全嵌入到片上密码系统中.采用流水线结构并用简单的异或电路来提高信息熵.该随机数发生器采用HJTC的0.18μm CMOS mixed signal工艺进行流片,并通过测试对其统计特性进行了分析.芯片功耗仅为1.42mW,输出比特率为10Mbit/s.     

新型抗振晶体振荡器的分析与设计

在车载和机载电子系统中,晶体振荡器在振动环境下的相位噪声性能发挥着重要作用。文中讨论了振动状态下晶体振荡器的相位噪声性能。采用双晶体谐振器设计了一种新型抗振晶体振荡器,从而实现了加速度灵敏度补偿。测试结果显示,加速度灵敏度补偿后的新型抗振晶体振荡器,在振动状态下的相位噪声可达-140 dBc/Hz＠1 kHz,性能得到20 dB以上的优化。因此,该方法在减小晶体振荡器的加速度、灵敏度方面均是可行且有效的。     

小型抗振晶体振荡器设计

在现代通信系统中,晶体振荡器的振动性能变得越发重要。文中讨论了振动状态下晶体振荡器的相位噪声性能,并通过采用微型减振器,设计了一种小型抗振晶体振荡器,从而提高晶体振荡器在振动状态下的相位噪声性能。测试结果显示,小型抗振晶体振荡器在振动状态下相位噪声达到-147 dBc/Hz@1 kHz,而相位噪声性能的优化可达40 dB。