Single electron transistor with P-type sidewall spacer gates

A single-electron transistor (SET) is one of the promising solutions to overcome the scaling limit of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). Up to now, various kinds of SETs are being proposed and SETs with a dual gate (DG) structure using an electrical potential barrier have been demonstrated for room temperature operation. To operate DG-SETs, however, extra bias of side gates is necessary. It causes new problems that the electrode for side gates and the extra bias for electrical barrier increase the complexity in circuit design and operation power consumption, respectively. For the reason, a new mechanism using work function (WF) difference is applied to operate a SET at room temperature by three electrodes. Its structure consists of an undoped active region, a control gate, n-doped source/drain electrodes, and metal/silicide or p-type silicon side gates, and a SET with metal/silicide gates or p-type silicon gates forms tunnel barriers induced by work function between an undoped channel and grounded side gates. Via simulation, the effectiveness of the new mechanism is confirmed through various silicide materials that have different WF values. Furthermore, by considering the realistic conditions of the fabrication process, SET with p-type sidewall spacer gates was designed, and its brief fabrication process was introduced. The characteristics of its electrical barrier and the controllability of its control gate were also confirmed via simulation. Finally, a single-hole transistor with n-type sidewall spacer gates was designed.     

Strain engineering of nanoscale Si P-type metal-oxide-semiconductor field-effect transistor devices with SiGe alloy integrated with contact-etch-stop layer stressors

Strained-silicon (Si) has been incorporated into a leading nanoscale logic technology. By means of silicon-germanium (SiGe) alloy stressor embedded in source and drain (S/D) region, the performance of P-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) is effectively enhanced. However, when a compressive contact-etch-stop layer (CESL) is combined, the stress interaction and relative impacts of SiGe stressor integrated with CESL on mobility enhancement has been little reported. Therefore, the research performs a three dimensional (3D) stress simulation evaluation based on finite element method (FEM) for PMOSFETs with S/D SiGe stressor and compressive CESL. The proposed simulation methodology is validated as compared with other technological literatures. In additions, the gate width dependency is systematically discussed to explore the stress effects on devices. The analysis results indicate that a -2.6 GPa CESL would continue boosting the stress magnitude on Si channel region except for a gate width smaller than 50 nm. The results are useful for nanoscale transistor while selecting a proper CESL in the manufacturing processes of advanced logic technologies.     

Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile

The effects of a nonuniform source/drain (S/D) doping profile on the FinFET characteristics are investigated using three-dimensional device simulation. With a fixed S/D doping profile, larger silicon-on-insulator (SOI) thickness can suppress short-channel effects due to the coexistence of longer channel regions. There can be some design margin in the channel thickness due to this reduced short-channel effect. Drain saturation current in FinFET is proportional to the effective device width and SOI thickness. To determine the appropriate SOI thickness of FinFET, alternating current (AC) characteristics are investigated. Device capacitance increases with SOI thickness, but this is not for the gate delay, as the drive current also increases and compensates for the increase of capacitance. When driving a constant capacitance load such as interconnect, devices with larger drain current or thicker SOI are more favorable for the fixed S/D doping condition.     

Gate-Induced Image Force Barrier Lowering in Schottky Barrier FETs

In this paper, we analyze the gate-induced image force barrier lowering in a 45-nm-gate-length ultra-thin-body silicon-on-insulator structure by using 2D full-band self-consistent ensemble Monte Carlo simulation with both tunneling current and thermal emission current. Results show that gate-induced barrier lowering has a very significant influence on the drive current. The influence of gate voltage, Schottky barrier height, spacer and channel doping concentration is also investigated and a theoretical analysis is presented.     

Reverse-order source/drain formation with double offset spacer (RODOS) for low-power and high-speed application

We proposed "reverse-order source/drain formation with double offset spacer" (RODOS) structure for low-power and high-speed applications. Both simulation and experimental data were used to evaluate the potential of the structure. It showed improved performance in terms of poly-depletion effect, dc characteristics, gate delay (CV/I), switching energy (CV/sup 2/) and linearity (V/sub IP3/). It satisfied all the requirements of LOP and LSTP for 90 nm technology node in ITRS 2002. Simulation predicted 794 /spl mu/A//spl mu/m in on-current, 0.1 nA//spl mu/m in off-current, 65 mV/V in DIBL, 80 mV/dec in SS, 1.29 ps in gate delay, 198 GHz in f/sub T/ and 0.151 fJ in switching energy in addition to enhanced linearity. Finally, we confirmed the high feasibility and potential of the RODOS MOSFET's for low-power and high-speed applications such as an LNA in portable communication appliances.     

The impact of structural parameters on the electrical characteristics of silicon nano wire transistor based on non equilibrium Green's function

In this paper we have used a fully ballistic quantum mechanical transport approach to analyse electrical characteristics of rectangular silicon nanowire field effect transistor in 7 nm gate length. We have investigated the impact of structural parameters of Gate all around Silicon nano wire transistor (GAA-SNWT) on its electrical characteristics in subthreshold regime. In particular we have shown the effect of increasing the Source/Drain and channel length (L(S), L(D) and L(Ch)) on short channel effects as well as change in body thickness and independent back gate voltage. We also investigate the effect of increasing the gate underlap on the electrical characteristics and on the switching speed of device. We show that if the Lun is increased the gate capacitance and DIBL will reduce while the I(ON)/I(OFF) ratio is increased.     

Formation of polycrystalline-Si thin-film transistors with tunneling field-effect-transistor structure

The formation of a poly-Si thin-film transistor (TFT) device with a tunneling field-effect-transistor (TFET) structure has been studied. With scaling the gate length down to 1 μm, the poly-Si TFT device with a conventional metal-oxide-semiconductor-field-effect-transistor structure would be considerably degraded, which exhibits an off-state leakage of about 10 nA/μm at a drain bias of 6 V. The short channel effect would tend to cause the source/drain punch-through and also increase the lateral electric field within the channel region, thus enhancing the carried field emission via trap states. The TFET structure can be employed to alleviate the short channel effect in the poly-Si TFT device. As a result, even for a gate length of 1 μm, the poly-Si TFT device with the TFET structure can exhibit an off-state leakage smaller than 1 pA/μm and an on/off current ratio of about eight orders at a drain bias of 7 V. Furthermore, even for a gate length of only 0.2 μm, the resultant poly-Si TFT device with the TFET structure can exhibit good electrical characteristics with an off-state leakage smaller than 10 pA/µm and an on/off current ratio of about six orders at a drain bias of 3.2 V. As a result, this scheme is promising for implementing a high packing density of poly-Si TFT devices.     

Electrical characteristics of nanoscale NAND silicon-oxide-nitride-oxide-silicon flash memory devices fabricated on SOI substrates

NAND silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with double gates fabricated on silicon-on-insulator (SOI) substrates were proposed. The current-voltage characteristics related to the programming operation of the designed nanoscale NAND SONOS flash memory devices on a SOI substrate and on the conventional bulk-Si substrate were simulated and compared in order to investigate device characteristics of the scaled-down memory devices. The simulation results showed that the short channel effect and the subthreshod leakage current for the memory device with a large spacer length were lower than that of the memory device with a small spacer length due to increase of the effective channel length. The device performance of the memory device utilizing the SOI substrate exhibited a smaller subthreshold swing and a larger drain current level in comparison with those on the bulk-Si substrate. These improved electrical characteristices for the SOI devices could be explained by comparing the electric field distribution in a channel region for both devices.     

Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics

We report a general approach for three-dimensional (3D) multifunctional electronics based on the layer-by-layer assembly of nanowire (NW) building blocks. Using germanium/silicon (Ge/Si) core/shell NWs as a representative example, ten vertically stacked layers of multi-NW field-effect transistors (FETs) were fabricated. Transport measurements demonstrate that the Ge/Si NW FETs have reproducible high-performance device characteristics within a given device layer, that the FET characteristics are not affected by sequential stacking, and importantly, that uniform performance is achieved in sequential layers 1 through 10 of the 3D structure. Five-layer single-NW FET structures were also prepared by printing Ge/Si NWs from lower density growth substrates, and transport measurements showed similar high-performance characteristics for the FETs in layers 1 and 5. In addition, 3D multifunctional circuitry was demonstrated on plastic substrates with sequential layers of inverter logical gates and floating gate memory elements. Notably, electrical characterization studies show stable writing and erasing of the NW floating gate memory elements and demonstrate signal inversion with larger than unity gain for frequencies up to at least 50 MHz. The ability to assemble reproducibly sequential layers of distinct types of NW-based devices coupled with the breadth of NW building blocks should enable the assembly of increasing complex multilayer and multifunctional 3D electronics in the future.     

Simulation study on a new dual-material nanowire MOS surrounding-gate transistor

In this paper, a novel field effect nanowire MOS transistor taking advantage of both dual-material gate and surrounding gate is proposed and performance characteristics are demonstrated numerically in detail. Surrounding-gate transistor is known to be used to enhance the electrostatic control of the channel, and dual-material-gate structure is extended from split-gate field effect transistor to obtain larger current and better short-channel performance. Three dimensional device simulations with Sentaurus Device are performed on this dual-material surrounding-gate transistor. Higher driving current, high ION/IOFF ratio and suppressed short-channel effects are obtained with this novel device structure.     

Extremely scaled 3-dimensional multiple-gate technologies for terabit era

In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel effects, punchthrough, source/drain series resistance, gate misalignment, and hot-carrier injection were intensively studied and optimized for the sub-5 nm structure. The sub-5 nm all-around gate FinFET with 3 nm fin width and 1.2 nm EOT was demonstrated for the first time.     

Retention characteristics of Schottky barrier tunneling transistor-nano floating gate memory with various side walls

At present, the nano floating gate memory (NFGM) device has shown a great promise as a ultra-dense, high-endurance memory device for low-power applications. As the size of the NFGM reduced, the short channel effect became one of the critical issues in the base Field Effect Transistor (FET). Schottky barrier tunneling transistor (SBTT) can improve the controllability of the short channel effect. In this work, we studied nano floating gate memory based on the SBTT. Erbium silicide was employed instead of the conventional heavily doped S/D. The NFGM device based on the SBTT used Si nanocrystals as charge storages. The subthreshold slope and the threshold voltage of the SBTT-NFGM were 90 mV/dec. and 0.2 V, respectively. The memory window appeared about 4 V after the applied write/erase bias at +/- 11 V for 500 ms. The write/erase speeds of the memory device were 50 ms and 200 ms at +/- 13 V, respectively. We also analyzed the retention characteristics of the Schottky barrier tunneling transistor nonvolatile floating gate memory according to the various side walls.     

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.     

Impact of strain engineering on nanoscale strained III-V PMOSFETs

Stress distributions in the strained InGaAs PMOSFET with source/drain (S/D) stressors for various lengths and widths were studied with 3D stress simulations. The resulting mobility improvement was analyzed. Compressive stress along the transport direction was found to dominate the hole mobility improvement for the wide width devices. Stress along the vertical direction perpendicular to the gate oxide was found to affect the mobility the least, while stress along the width direction enhanced in the middle wide width region. The impact of channel width and length on performance improvements such as the mobility gain was analyzed using the Kubo-Greenwood formalism accounting for nonpolar hole-phonon scattering (acoustic and optical), surface roughness scattering, polar phonon scattering, alloy scattering and remote phonon scattering. The novelty of this paper is studying the impact of channel width and length on the performance of InGaAs PMOSFET such as mobility and exploring physical insight for scaling the future III-V CMOS devices.     

A dual-gate-controlled single-electron transistor using self-aligned polysilicon sidewall spacer gates on silicon-on-insulator nanowire

A dual-gate-controlled single-electron transistor was fabricated by using self-aligned polysilicon sidewall spacer gates on a silicon-on-insulator nanowire. The quantum dot formed by the electric field effect of the dual-gate structure was miniaturized to smaller than the state-of-the-art feature size, through a combination of electron beam lithography, oxidation, and polysilicon sidewall spacer gate formation processes. The device shows typical MOSFET I-V characteristics at room temperature. However, the Coulomb gap and Coulomb oscillations are clearly observed at 4 K.     

PDSOI NMOS/CMOS闩锁特性

本文研究了部分耗尽绝缘体上的硅(PDSOI)NMOS、CMOS结构的闩锁(latch)特性。提出了一种体电极触发诱发PDSOI NMOS器件闩锁效应维持电压的测试方法,并用此方法测试出了不同栅长、栅宽和体接触结构NMOS/CMOS的闩锁效应维持电压,以及沟道注入条件和温度对维持电压的影响。     

Formation of polycrystalline thin-film transistors with stacked poly-SiGe/poly-Si channel layer for low-voltage applications

A thin-film transistor (TFT) with polycrystalline SiGe/Si stacked channel layer has been proposed for low-voltage applications. For the stacked poly-SiGe/poly-Si channel layer, the resultant 1-μm TFT device can achieve an on/off current ratio above 7 orders and a relatively large on-state current at a low operating voltage, and also cause better transfer characteristics than both the conventional poly-Si and poly-SiGe channel layers. As compared to the poly-Si channel layer, the poly-SiGe channel layer may cause a larger on-state current at a small gate bias of 3 V, due to smaller difference between conduction band and intrinsic level. However, even at a small drain bias of 3 V, the poly-SiGe channel layer leads to an off-state leakage current of about 2 order larger than the poly-Si channel layer, since a smaller energy bandgap may cause more carrier field emission via trap states. As a result, when a poly-SiGe/poly-Si stacked channel layer is employed, the leakage current may be suppressed to a low level as that for the poly-Si channel layer, and the resultant on-state current at a low gate bias voltage can be close to a relatively high level as that for the poly-SiGe channel layer.     

High-Performance Si Nanowire Transistors on Fully Si Bulk Substrate From Top-Down Approach: Simulation and Fabrication

A new method to fabricate high-performance gate-all-around silicon (Si) nanowire transistors (SNWTs) based on fully Si bulk (FSB) substrate is proposed and demonstrated by both simulation and experiments in this paper. Due to the large fan-out and deep junction of Si source/drain (S/D) region connecting with the bulk substrate, the FSB SNWTs can effectively alleviate the self-heating effects with technology scaling. Thermal behavior of multiwire SNWTs is investigated and FSB SNWTs show superior self-heating immunity to SNWTs based on Si-on-insulator (SOI) substrate (SOI SNWTs). In addition, the bottom parasitic transistor can be well suppressed in this structure. Although FSB SNWTs have larger gate parasitic capacitance, the CV/ $I$ is found to be comparable to the SOI SNWTs. With self-aligned, fully epi-free compatible CMOS processes, this new architecture was successfully fabricated, which exhibit high on–off current ratio of $hbox{2.6} times hbox{10}^{8}$ due to better heat dissipation and low S/D resistance realized in this structure.      

Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage

Near ballistic n-type single-walled carbon nanotube field-effect transistors (SWCNT FETs) have been fabricated with a novel self-aligned gate structure and a channel length of about 120 nm on a SWCNT with a diameter of 1.5 nm. The device shows excellent on- and off-state performance, including high transconductance of up to 25 microS, small subthreshold swing of 100 mV/dec, and gate delay time of 0.86 ps, suggesting that the device can potentially work at THz regime. Quantitative analysis on the electrical characteristics of a long channel device fabricated on the same SWCNT reveals that the SWCNT has a mean-free-path of 191 nm, and the electron mobility of the device reaches 4650 cm(2)/Vs. When benchmarked by the metric CV/ I vs Ion/Ioff, the n-type SWCNT FETs show significantly better off-state leakage than that of the Si-based n-type FETs with similar channel length. An important advantage of this self-aligned gate structure is that any suitable gate materials can be used, and in particular it is shown that the threshold voltage of the self-aligned n-type FETs can be adjusted by selecting gate metals with different work functions.     

An investigation of contact resistance between metal electrodes and amorphous gallium-indium-zinc oxide (a-GIZO) thin-film transistors

This paper reports our investigation of different source/drain (S/D) electrode materials in thin-film transistors (TFTs) based on an indium-gallium-zinc oxide (IGZO) semiconductor. Transfer length, contact resistance, channel conductance, and effective resistances between S/D electrodes and amorphous IGZO thin-film transistors were examined. Intrinsic TFT parameters were extracted by the transmission line method (TLM) using a series of TFTs with different channel lengths measured at a low drain voltage. The TFTs fabricated with Cu S/D electrodes showed the lowest contact resistance and transfer length indicating good ohmic characteristics, and good transfer characteristics with intrinsic field-effect mobility (μ_FE-i) of 10.0 cm²/Vs.