Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

Fabrication of silicon and oxide membranes over cavities usingion-cut layer transfer

Silicon and oxide membranes were fabricated using an ion-cut layer transfer process, which is suitable for sub-micron-thick membrane fabrication with good thickness uniformity and surface micro-roughness. After hydrogen ions were implanted into a silicon wafer, the implanted wafer was bonded to another wafer that has patterned cavities of various shapes and sizes. The bonded pair was then heated until hydrogen-induced silicon layer cleavage occurred along the implanted hydrogen peak concentration, resulting in the transfer of the silicon layer from one wafer to the other. Using this technique, we have been able to form sealed cavities and channels of various shapes and sizes up to 50-μm wide, with a 1.6-μm-thick silicon membrane. As a process variation, we have also fabricated silicon dioxide membranes for optically transparent applications     

Non-destructive in situ test for anodic bonding

New test structures have been designed, fabricated and tested to monitor the quality of the anodic bonding between silicon and glass. The main advantage of the described test is that it is not destructive and allows the bond quality to be monitored in processed wafers. This test is very easy to implement in a chip or in a wafer because of its simplicity. Test structures consist of a matrix of circular and rectangular cavities defined by reactive ion etching (RIE) on the silicon wafer, with different sizes and depths. The bonding process and quality can be monitorized by the measurement of the size of the smallest bonded cavity and the distance between the bonded area and the cavity border. These structures give information about the level of electrostatic pressure that has been applied to pull together into intimate contact the surfaces of the two wafers. The higher the electrostatic pressure, the better the bond. We have applied these test structures to study the influence of the voltage and the temperature on the anodic bonding process. Results are in good agreement with finite-element method (FEM) simulations.     

A dielectrophoretic chip packaged at wafer level

The paper presents a dielectrophoretic chip, fully enclosed, with bulk silicon electrodes fabricated using wafer-to-wafer bonding techniques and packaged at the wafer level. The silicon electrodes, which are bonded to two glass dies, define in the same time the walls of the microfluidic channel. The device is fabricated from a silicon wafer that is bonded (at wafer level) anodically and using SU8 photoresist between two glass wafers. The first glass die includes drilled holes for inlet/outlet connections while the second glass die assure the electrical connections, through via holes and a metallization layer, between the silicon electrodes and a printing circuit board.     

A dielectrophoretic chip packaged at wafer level

The paper presents a dielectrophoretic chip, fully enclosed, with bulk silicon electrodes fabricated using wafer-to-wafer bonding techniques and packaged at the wafer level. The silicon electrodes, which are bonded to two glass dies, define in the same time the walls of the microfluidic channel. The device is fabricated from a silicon wafer that is bonded (at wafer level) anodically and using SU8 photoresist between two glass wafers. The first glass die includes drilled holes for inlet/outlet connections while the second glass die assure the electrical connections, through via holes and a metallization layer, between the silicon electrodes and a printing circuit board.

     

Versatile low temperature wafer bonding and bond strength measurement by a blister test method

We present a low temperature plasma assisted bonding process that enables the bonding of silicon, silicon oxide and silicon nitride wafers among each other at annealing temperatures as low as room temperature. The process can be applied using standard clean room equipment. Surface energies of differently treated bonded samples are determined by a blister test method for square shaped cavities. For this reason, we extend the well-known blister test method for round shaped cavities to the square shaped case by a combined analytical and numerical approach. Accordingly, the energetic favored crack front propagation in the bond interface is determined by numerical simulations. The surface energies of the tested samples are calculated and compared to anodic silicon-to-Pyrex^® bonds. Surface energies of up to 2.6 J/m² can be achieved between silicon and silicon oxide wafer pairs at low annealing temperatures. Room temperature bonded samples show a surface energy of 1.9 J/m². The surface energy of silicon-to-Pyrex glass bonds yields 1.3 J/m². Small structures, e.g., bridges down to 5 μm can be bonded using the discussed bonding process. Selective bonding of silicon-to-silicon oxide wafer pairs is performed by structuring the oxide layer. The successful integration of the bonding process into the fabrication of micropumps is highlighted.     

Fluid flows in microchannels with cavities

Pressure-driven gas and liquid flows through microchannels with cavities have been studied using both experimental measurements and numerical computations. Several microchannels with cavities varying in shape, number and dimensions have been fabricated. One set of microdevices, integrated with sensors on a silicon wafer, is used for flow rate and pressure distribution measurements in gas flows. Another set of microdevices, fabricated using glass-to-silicon wafer bonding, is utilized for visualization of liquid flow patterns. The cavity effect on the flow in the microchannel is found to be very small, with the mass flow rate increasing slightly with increasing number of cavities. The flow pattern in the cavity depends on two control parameters; it is fully attached only if both the reduced Reynolds number and the cavity number are small. A flow regime map has been constructed, where the critical values for the transition from attached to separated flow are determined. The numerical computations reveal another control parameter, the cavity aspect ratio. The flow in the cavity is similar only if all three control parameters are the same. Finally, the vorticity distribution and related circulation in the cavity are analyzed. [1546].     

Design of sealed cavity microstructures formed by silicon waferbonding

Three fabrication issues related to the design and fabrication of micromechanical devices using sealed cavities within bonded silicon wafers are discussed. The first concerns the resultant residual gas pressure within a sealed cavity between two bonded wafers after bonding and a high-temperature anneal. The second concerns the prediction of plastic deformation in capping layers of single-crystal silicon over sealed cavities. Exposure of sealed cavity structures to a high-temperature environment causes the trapped residual gas to expand, which can result in the plastic deformation of the capping layer. A model for analytically predicting the occurrence of plastic deformatio in these silicon capping layers has been developed. The third fabrication issue concerns the prediction of the resultant height of plastically deformed capping layers of silicon after cooling. A model which gives a lower and an upper bound on the height, based on an analytical spherical shell membrane stress equation, has been developed     

Micromachined flat-walled valveless diffuser pumps

The first valveless diffuser pump fabricated using the latest technology in deep reactive ion etching (DRIE) is presented. The pump was fabricated in a two-mask micromachining process in a silicon wafer polished on both sides, anodically bonded to a glass wafer. Pump chambers and diffuser elements were etched in the silicon wafer using DRIE, while inlet and outlet holes are etched using an anisotropic etch. The DRIE etch resulted in rectangular diffuser cross sections. Results are presented on pumps with different diffuser dimensions in terms of diffuser neck width, length, and angle. The maximum pump pressure is 7.6 m H₂O (74 kPa), and the maximum pump flow is 2.3 ml/min for water     

A bulk silicon dissolved wafer process for microelectromechanicaldevices

A single-sided bulk silicon dissolved wafer process that has been used to fabricate several different micromechanical structures is described. It involves the simultaneous processing of a glass wafer and a silicon wafer, which are eventually bonded together electrostatically. The silicon wafer is then dissolved to leave heavily boron doped devices attached to the glass substrate. Overhanging features can be fabricated without additional masking steps. It is also possible to fabricate elements with thickness-to-width aspect ratios in excess of 10:1. Measurements of various kinds of laterally driven comb structures processed in this manner, some of which are intended for application in a scanning thermal profilometer, are described. They comprise shuttle masses supported by beams that are 160-360 μm long, 1-3 μm wide, and 3-10 μm thick. Some of the shuttles are mounted with probes that overhang the edge of the die by 250 μm. Resonant frequencies from 18 to 100 kHz and peak-to-peak displacements up to 18 μm have been measured     

Development of near hermetic silicon/glass cavities for packaging of integrated lithium micro batteries

A technology was developed for fabrication of very thin, chip-sized lithium secondary micro batteries. With help of wafer level processing the batteries can be directly integrated into silicon chips or MEMS devices. The batteries were packaged in 200 μm deep cavities of the silicon wafer and encapsulated with a glass substrate. Battery demonstrators were realized with 7 and 12 mm square and round foot prints. Near hermetic packaging was accomplished with the help of a UV curable epoxy seal that should ensure several years of battery lifetime. Bonding parameters, shear force and the water permeation rate of the adhesive were investigated. A capacity of 3 mAh/cm² and an energy density of 10 mWh/cm² were achieved. The electrical contact between the battery and the contact pads of the housing was investigated in detail. Electrical tests were made with encapsulated micro batteries and compared with macroscopic lithium polymer batteries. A reduction in capacity of approximately 10% was measured after 100 cycles.     

A new method for fast anodic bonding in microsystem technology

Other than temperature and voltage, load plays a key role in anodic bonding process. In this paper we present a new design of top electrode (cathode) for anodic bonding machine by which the bonding time has been reduced up to 30 % in case of bare silicon wafer at ?400 V and approximate 52 % in case of oxidized silicon wafer with Pyrex glass bonding at ?800 V. Experimentally it has been observed there was no bonding in oxidized silicon wafer with Pyrex glass up to ?600 V by using standard design while it has been successfully bonded at same voltage (?600 V) by using new design.     

A low-cost through via interconnection for ISM WLP

Wafer level packaging (WLP) for image sensor device has the advantage of small size, high performance and low cost. In WLP technology, in order to form electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed, such as T-contact and through silicon via (TSV). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and increase yield of image sensor packaging. Key fabrication processes includes glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on the backside of CMOS image sensor wafer, only small opening area is need for making via interconnection with vertical sidewall presented in this paper. A fillet structure at bottom corner of via holes can help to reduce sequent process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation. The through via interconnection shows good electrical connection performance, and high-quality photo images are obtained by packaged image sensor device.     

Room-Temperature Sealing of Microcavities by Cold Metal Welding

In this paper, we present a wafer-to-wafer attachment and sealing method for wafer-level manufacturing of microcavities using a room-temperature bonding process. The proposed attachment and sealing method is based on plastic deformation and cold welding of overlapping metal rings to create metal-to-metal bonding and sealing. We present the results from experiments using various bonding process parameters and metal sealing ring designs including their impact on the resulting bond quality. The sealing properties against liquids and vapor of different sealing ring structures have been evaluated for glass wafers that are bonded to silicon wafers. In addition, wafer-level vacuum sealing of microcavities was demonstrated when bonding a silicon wafer to another silicon wafer with the proposed room-temperature sealing and bonding technique.$hfill$ [2008-0053]      

微创手术式硅微机械加工（MISSM）技术

介绍了一种新颖的微创手术式硅微机械加工(MISSM)技术,该技术充分利用(111)硅片的晶向分布和各向异性湿法腐蚀的特性。通过在单晶硅片表面制作一系列微型释放窗口来定义结构的轮廓及尺寸,实现在单晶硅片内部选择性可自停止腐蚀技术,制作出不同结构尺寸的腔体。同时,结合不同器件结构设计的需求,缝合微型释放窗口并进行后续工艺制作及最终可动结构释放。该技术采用微创手术式单硅片单面体硅工艺替代传统的表面微机械工艺,制作工艺简单,既具有单硅片单面加工的优势又便于与IC工艺兼容。文章详细讲述了微创手术式三维微机械结构的成型机理和工艺流程,并针对其关键技术进行了系统的分析,取得了令人满意的结果。     

Micromachining of buried micro channels in silicon

A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the sidewalls of the trench, removal of the coating at the bottom of the trench, and etching into the bulk of the silicon substrate. The structures can be sealed by deposition of a suitable layer that closes the trench. BCT is a process that can be used to fabricate complete micro channels in a single wafer with only one lithographic mask and processing on one side of the wafer, without the need for assembly and bonding. The process leaves a substrate surface with little topography, which easily allows further processing, such as the integration of electronic circuits or solid-state sensors. The essential features of the technology, as well as design rules and feasible process schemes, will be demonstrated on examples from the field of μ-fluidics     

A study of an autonomous mobile robot in an outdoor environment

This paper describes an experimental study of the fabrication of micro-mechanisms on a silicon wafer. Planar process technology developed in the industry of CMOS LSI was employed. The structural material is CVD-polycrystalline silicon with a thickness of 2.5 μm and the sacrificial material is CVD-SiO₂ with a thickness of 1.0 μm. In the experimental study, micro-rotors with a shaft and a cap in an assembled form were fabricated on a silicon wafer. The self-alignment process gave a tolerance of 1.0 μm between the rotor and the shaft. The maximum rotation speed observed was 9 x 10⁴ rpm by blowing nitrogen gas.     

Lithography with high depth of focus by an ion projection system

Ion projection lithography is developed to generate structures with minimum feature sizes in the 100-nm range with a high pixel transfer rate. The high depth of focus (DOF) resulting from the telecentric beam path concept is also noteworthy. A silicon wafer exhibiting 200-μm-deep cavities, which are fabricated by anisotropic etching, is patterned with a grating of 0.6 μm periodicity running with identical spacings from the bottom to the top. SiO₂ serves as an inorganic ion sensitive resist. Exposed to 73 keV helium ions, SiO₂ shows an enhanced etching rate in hydrofluoric acid, the structure developing agent. The patterning techniques considered are promising for the fabrication of two-dimensional reflecting mirrors or sensoric elements distributed on spherical surfaces     

A two-step etching method to fabricate nanopores in silicon

A cost effective method to fabricate nanopores in silicon by only using the conventional wet-etching technique is developed in this research. The main concept of the proposed method is a two-step etching process, including a premier double-sided wet etching and a succeeding track-etching. A special fixture is designed to hold the pre-etched silicon wafer inside it such that the track-etching can be effectively carried out. An electrochemical system is employed to detect and record the ion diffusion current once the pre-etched cavities are etched into a through nanopore. Experimental results indicate that the proposed method can cost effectively fabricate nanopores in silicon. A through pore with pore size being around 14 nm can be fabricated.     

Low-temperature anodic bonding of silicon to silicon wafers by means of intermediate glass layers

Silicon wafers have been anodically bonded to sputtered lithium borosilicate glass layers (Itb 1060) at temperatures as low as 150–180 °C and to sputtered Corning 7740 glass layers at 400 °C. Dependent on the thickness of the glass layer and the sputtering rate, the sputtered glass layers incorporate compressive stresses which cause the wafer to bow. As a result of this bowing, no anodic bond can be established especially along the edges of the silicon wafer. Successful anodic bonding not only requires plane surfaces, but also is determined very much by the alkali concentration in the glass layer. The concentration of alkali ions as measured by EDX and SNMS depends on both the sputtering rate and the oxygen fraction in the argon process gas. In Itb 1060 layers produced at a sputtering rate of 0.2 nm/s, and in Corning 7740 layers produced at sputtering rates of 0.03 and 0.5 nm/s, respectively, the concentration of alkali ions in the glass layers was sufficiently high, at oxygen partial pressures below 10^-4 Pa, to achieve anodic bonding. High-frequency ultrasonic microanalysis allowed the bonding area to be examined non-destructively. Tensile strengths between 4 and 14 MPa were measured in subsequent destructive tensile tests of single-bonded specimens.