Development of no-flow underfill materials for lead-free solderbumped flip-chip applications

No-flow underfill process in flip-chip assembly has become a promising technology toward a smaller, faster and more cost-efficient packaging technology. The current available no-flow underfill materials are mainly designed for eutectic tin-lead solders. With the advance of lead-free interconnection due to the environmental concerns, a new no-flow underfill chemistry needs to be developed for lead-free solder bumped flip-chip applications. Many epoxy resin/hexahydro-4-methyl phthalic anhydride/metal acetylacetonate material systems have been screened in terms of their curing behavior. Some potential base formulations with curing peak temperatures higher than 200°C (based on differential scanning calorimetry at a heating rate of 5°C/min) are selected for further study. The proper fluxing agents are developed and the effects of fluxing agents on the curing behavior and cured material properties of the potential base formulations are studied using differential scanning calorimetry, thermomechanical analysis, dynamic-mechanical analysis, thermogravimetric analysis, and rheometer. Fluxing capability of the developed no-flow formulations is evaluated using the wetting test of lead-free solder balls on a copper board. The developed no-flow underfill formulations show sufficient fluxing capability and good potential for lead-free solder bumped flip-chip applications     

Gallium alloy interconnects for flip-chip assembly applications

For miniature interconnection applications, innovative material systems based on gallium alloys offer potentially attractive alternatives over commonly used bonding materials, such as solders and conductive adhesives, without the reliability and environmental drawbacks. Gallium alloys are mechanically alloyed mixtures of a liquid metal and metallic powders, formed at room temperature. The alloys cure to form solid intermetallic compounds. In this work, gallium alloys have been investigated for flip-chip interconnect applications. Specifically, this paper presents the results of a preliminary feasibility study demonstrating gallium alloys as advanced interconnect materials for flip-chip on laminate applications. The topics covered include the test vehicle assembly process, reliability screening results, preliminary failure mode analysis, and interconnect microstructure analysis. To demonstrate preliminary feasibility and application, gallium alloyed with copper and nickel was used as micro-miniature interconnects between bare silicon chips and printed circuit boards. This study shows preliminary feasibility of such interconnects and reliability tests demonstrate reasonable cyclic fatigue with the use of underfill. Moreover, through the course of this work a new micro-deposition technology for gallium alloys was developed which leverages existing industry infrastructure. This initial study represents a significant advancement in microelectronic interconnect materials unveiling the potential for an innovative lead-fine, low-temperature interconnect alternative     

Design rule development for microwave flip-chip applications

This paper presents a novel experimental approach for the analysis of factors to be considered when designing a flip-chip package. It includes the design of an experiment and statistical analysis of the outputs and uses both test-structure measurements and full-wave simulation techniques in the 1-35-GHz frequency range. The most significant factors are found to be, from the most to least important, the length of the area where the device and substrate overlap (referred to as conductor overlap), the bump diameter, and the width of the coplanar-waveguide transmission-line launch. These results are valid for conductor overlaps between 300-500 μm. For a lower value (120 μm), the significance level of the overlap decreases and the bump height also becomes significant. Test-structure measurements in the 120-200-μm overlap range validate this result and demonstrate the decrease in the significance level. The substrate thickness in the 10-25-mil interval is found to be statistically insignificant, therefore, it can be eliminated from further analysis. This approach provides a foundation for development of a set of design rules for RF and microwave flip-chip similar to RF integrated-circuit design rules     

Evaluation of Cu-bumps with lead-free solders for flip-chip package applications

Low cost electroplated Cu-bump with environmental friendly Sn solder was developed for flip-chip applications. The seed layer used was Ti/WN_x/Ti/Cu where WN_x was used as the Cu diffusion barrier and Ti was used to enhance the adhesion between bump and the chip pad. Thick negative photoresist (THB JSR-151N) with a high aspect ratio of 2.4 was used for electroplating of copper bump and Sn solder. The Sn solder cap was reflowed at 225° for 6 min at N₂ atmosphere. No wetting phenomenon was observed for the Sn solder as evaluated by energy-dispersed spectroscopy (EDS). The Cu-bump with Ti/WN_x/Ti/Cu seed layer not only have higher shear force than the Cu-bump with Ti/Cu seed layer but also has higher resistance to fatigue failure than the Au, SnCu, SnAg bumps.     

An improvement of thermal conductivity of underfill materials for flip-chip packages

Effective heat dissipation is crucial to enhance the performance and reliability of electronic devices. In this work, the performance of encapsulants filled with carbon fiber was studied and compared with silica filled encapsulants. Encapsulants filled with mixed combination of fillers for optimizing key properties were also investigated. The thermal and electrical conductivities were investigated and glass transition temperature (Tg), thermal expansion coefficient (TCE), and storage modulus (E') of these materials were studied with thermal analysis methods. The composites filled with both carbon fiber and silica showed an increase of thermal conductivity three to five times of that of silica filled encapsulants of the same filler loading while maintaining/enhancing major mechanical and thermal properties.     

Effects of silica filler and diluent on material properties and reliability of nonconductive pastes (NCPs) for flip-chip applications

In this paper, thermomechanical and rheological properties of nonconductive pastes (NCPs) depending on silica filler contents and diluent contents were investigated. And then, thermal cycling (T/C) reliability of flip chip assembly using selected NCPs was verified. As the silica filler content increased, thermomechanical properties of NCPs were changed. The higher the silica filler content was added, glass transition temperature (T/sub g/) and storage modulus at room temperature became higher while coefficient of thermal expansion (CTE) decreased. On the other hand, rheological properties of NCPs were significantly affected by diluent content. As the diluent content increased, viscosity of NCP decreased and thixotropic index increased. However, the addition of diluent deteriorated thermomechanical properties such as modulus, CTE, and T/sub g/. Based on these results, three candidates of NCPs with various silica filler and diluent contents were selected and used as adhesives for reliability test of flip chip assemblies. T/C reliability test was performed by measuring changes of NCP bump connection resistance. Results showed that flip chip assembly using NCP with lower CTE and higher modulus exhibited better T/C reliability behavior because of reduced shear strain in NCP adhesive layer.     

Modeling of the curing kinetics of no-flow underfill in flip-chip applications

No-flow underfill has greatly improved the production efficiency of flip-chip process. Due to its unique characteristics, including reaction latency, curing under solder reflow conditions and the desire for no post-cure, there is a need for a fundamental understanding of the curing process of no-flow underfill. Starting with a promising no-flow underfill formulation, this paper seeks to develop a systematic methodology to study and model the curing behavior of this underfill. A differential scanning calorimeter (DSC) is used to characterize the heat flow during curing under isothermal and temperature ramp conditions. A modified autocatalytic model is developed with temperature-dependent parameters. The degree of cure (DOC) is calculated; compared with DSC experiments, the model gives a good prediction of DOC under different curing conditions. The temperature of the printed wiring board (PWB) during solder reflow is measured using thermocouples and the evolution of DOC of the no-flow underfill during the reflow process is calculated. A stress rheometer is used to study the gelation of the underfill at different heating rates. Results show that at high curing temperature, the underfill gels at a lower DOC. Based on the kinetic model and the gelation study, the solder wetting behavior during the eutectic SnPb and lead-free SnAgCu reflow processes is predicted and confirmed by the solder wetting tests.     

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.     

偶联剂处理对吸波材料电磁特性影响的研究进展

偶联剂是常见的表面改性剂,广泛应用在复合材料表面改性处理领域,其应用于吸波材料表面改性的技术也是吸波材料的研究热点之一。首先总结了制备方法、偶联剂的种类和添加量这些因素对偶联剂改性吸波材料电磁特性影响的研究现状,然后分析了这些因素对吸波材料的电磁参量调控的重要作用,最后展望了偶联剂处理技术改善吸波材料吸波性能的未来前景。     

Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7/spl deg/C. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps.     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

Packaging properties of ALIVH-CSP using SBB flip-chip bondingtechnology

A new chip scale package (CSP) using an organic laminated substrate called μCSP was developed, which was fabricated using ALIVH substrate as a interposer and stud-bump-bonding (SBB) flip-chip technology. The ALIVH substrate is a multilayered organic substrate with inner via holes in any layer. The newly developed CSP-L using ALIVH substrate realized a miniaturization of its package size to the same as a CSP using a ceramic substrate (CSP-C). In order to perform the SBB flip-chip bonding onto the ALIVH substrate, an excellent coplanarity of the substrate surface was required. The required coplanarity was obtained using a fixture during the SBB flip-chip bonding process. The first-level packaging reliability and the second-level packaging reliability onto ALIVH mother board were evaluated. The resulting reliabilities were good enough to apply to practical use     

Effect of silver content on the shear fatigue properties of Sn-Ag-Cu flip-chip interconnects

The mechanical shear fatigue test has been performed to study the effect of silver content on the fatigue properties of Sn-xAg-0.5Cu (x=1, 2, 3, and 4) for flip-chip interconnections. The strength of the solder alloy increases with increasing silver content, preventing shear plastic deformation of the solder bump. The flip-chip joints made using higher silver content solder, such as 3%Ag and 4%Ag, exhibit longer fatigue life for all conditions. The fatigue ductility of the solder decreases with an increase in the silver content. The fatigue endurance of 1%Ag solder is superior to other solders over the plastic strain range of 3%, even though the strength of the solder is the lowest in the solders tested. Based on this study, the 3Ag solder may exhibit good fatigue performance for all conditions, and the 1Ag solder is optimum for severe strain conditions.     

Study of a dipping method for flip-chip flux coating

A dipping method for flux coating is proposed in the paper. Flow process of the flux transferred into the groove is investigated by using an optical detection means. Flow process influenced by gluing speed and viscosity is analyzed by using two indicators including reflective area ratio and flow velocity. Experimental result shows that stably reflective area ratio of glue is associated with gluing speed instead of viscosity; and it decreases with the increase of gluing speed in a same viscosity. The reason is that different gluing speed changes the amount of the glue transferred to the groove. Flow velocity of glue is related with gluing speed, a greater gluing speed leads to greater maximum flow velocity at the same viscosity, which may be due to larger gluing speed gives greater inertial force to the glue. Real chip experiments verified the feasibility of this method.     

Study of package warp behavior for high-performance flip-chip BGA

To meet the future needs of high pin count and high performance, the LSI die and package size of flip-chip BGA (FC-BGA) devices have become larger. As a result, package warpage due to mismatch of the coefficients of thermal expansion among the construction materials has become a more serious problem for package reliability. In this paper, package warpage is successfully measured by a 3-D surface profile method in the temperature range from −55 to 230 °C. Furthermore, the package warpage of FC-BGA was investigated to clarify the effect of the thermomechanical properties of the underfill resin. Based on the results, we constructed a model of the mechanism of package warpage. This paper proposes an optimized underfill resin that can achieve low package warpage and a long fatigue life of the solder bump. The future trends in underfill resin will be to have properties of extremely low elastic modulus and non-linear properties such as creep.     

Annealing effects on physical properties of doped CdTe thin films for photovoltaic applications

Polycrystalline Cadmium Telluride (CdTe) thin films were prepared on glass substrates by thermal evaporation at the chamber ambient temperature and then annealed for an hour in vacuum ~1×10⁻⁵ mbar at 400 °C. These annealed thin films were doped with copper (Cu) via ion exchange by immersing these films in Cu (NO₃)₂ solution (1 g/1000 ml) for 20 min. Further these films were again annealed at different temperatures for better diffusion of dopant species. The physical properties of an as doped sample and samples annealed at different temperatures after doping were determined by using energy dispersive x-ray analysis (EDX), x-ray diffraction (XRD), Raman spectroscopy, transmission spectra analysis, photoconductivity response and hot probe for conductivity type. The optical band gap of these thermally evaporated Cu doped CdTe thin films was determined from the transmission spectra and was found to be in the range 1.42–1.75 eV. The direct energy band gap was found annealing temperatures dependent. The absorption coefficient was >10⁴ cm⁻¹ for incident photons having energy greater than the band gap energy. Optical density was observed also dependent on postdoping annealing temperature. All samples were found having p-type conductivity. These films are strong potential candidates for photovoltaic applications like solar cells.     

Electrical and acoustic properties of biological materials and biomedical applications

A survey of our research on the linear electrical and acoustic properties of biological materials including cells, tissues, and biopolymers is presented. Topics include: 1) dielectric properties of tissues and cells from dc to 20 GHz; 2) identification of the mechanism responsible for major dielectric relaxation effects observed (counter ion relaxation, Maxwell?Wagner charging of membrane interfaces, relaxation of protein bound water, and relaxation of tissue water); 3) ultrasonic properties of biopolymers and tissues (identification of macromolecular absorption as the dominant contributor to acoustic absorption); and 4) interaction of EM fields with biosystems. This, in turn, includes applications in physical medicine, investigations of field-induced force effects on cells and their response, macroscopic and microscopic dosimetry, development of safety standards, and applications of available biophysical insight to evaluate field interaction with cells, membranes, and macromolecules.     

Infrared materials for thermophotovoltaic applications

Thermophotovoltaic generation of electricity is attracting renewed attention due to recent advances in low bandgap (0.5–0.7 eV) III-V semiconductors. The use of these devices in a number of applications has been reviewed in a number of publications.^1–4 Two potential low-bandgap diode materials are In_xGa_1−xAs_ySb_1−y and In_xGa_1−xAs. The performance of these devices are comparable (quantum efficiency, open circuit voltage, fill factor) despite the latter’s long-term development for optoelectronics. For an 1100°C blackbody, nominally 0.55 eV devices at 25°C exhibit average photon-weighted internal quantum efficiencies of 70–80%, open circuit voltage factors of 60–65%, and fill factors of 65–70%. Equally important as the energy conversion device is the spectral control filter that effectively transmits above bandgap radiation into the diode and reflects the below bandgap radiation back to the radiator. Recent developments in spectral control technology, including InGaAs plasma filters and nonabsorbing interference filters are presented. Current tandem filters exhibit spectral utilization factors of ∼65% for an 1100°C blackbody.     

Study on the relationship between the surface composition of copperpads and no-flow underfill fluxing capability

The purpose of this paper is to investigate the effect of copper pad surface composition on the wetting of solder bumps during reflow process for a certain no-flow underfill material. A purchased copper foil which is laminated on FR4 board is used as a control surface. Six different procedures are followed to prepare the surface of the copper foil with six different compositions. XPS is then used to analyze the surface compositions of the six surfaces and the control surface. An in-house developed G25 no-flow underfill encapsulant is used to examine the wetting status of eutectic solder balls on these copper surfaces. The correlation of the copper surface compositions with the solder wetting is then established. It is verified that the compositions of the copper foil surfaces strongly depend on the cleaning procedures. For G25 no-flow underfill material, copper oxide (CuO) is the main composition that prevents the solder ball from wetting the copper foils while the observed organic contamination does not have noticeable effect on the solder wetting