硅基光子集成宽带大色散延时芯片（特邀）

集成、宽带、大色散延时的器件在微波光子滤波、真延时相控阵天线等领域有着重要的应用,可以有效地降低系统尺寸和功耗。文中提出并实现了一种基于硅基光子集成的宽带大色散延时芯片,通过采用超低损耗波导结构和侧壁法向量调制结构实现了片上集成大色散波导光栅,色散值超过250 ps/nm, 最大群延时达到2440 ps,带宽大于9.4 nm,该芯片有望用于微波光子学、高速光纤通信系统等领域。     

Wireless communication in a flip-chip package using integrated antennas on silicon substrates

An intrachip wireless interconnect using integrated antennas is demonstrated in a flip-chip ball grid array package. The wireless interconnect consists of a transmitter-receiver pair, which is fabricated in a 0.18-/spl mu/m CMOS process. A 15-GHz signal is generated and broadcasted across the integrated circuit. The signal is picked up by a receiver 4 mm away on the same integrated circuit and frequency divided by eight to produce a 1.875-GHz local clock signal. The interconnection is also demonstrated between a transmitting antenna and a packaged receiver 40 cm away from the transmitting antenna. Demonstration of intrachip wireless interconnects in a package has been considered the ultimate test for this technology.     

Intra-chip wireless interconnect for clock distribution implementedwith integrated antennas, receivers, and transmitters

A wireless interconnect system which transmits and receives RF signals across a chip using integrated antennas, receivers, and transmitters is proposed and demonstrated. The transmitter consists of a voltage-controlled oscillator, an output amplifier, and an antenna, while the receiver consists of an antenna, a low-noise amplifier, a frequency divider, and buffers. Using a 0.18-μm CMOS technology, each of these individual circuits is demonstrated at 15 GHz. Wireless interconnection for clock distribution is then demonstrated in two stages. First, a wireless transmitter with integrated antenna generates and broadcasts a 15-GHz global clock signal across a 5.6-mm test chip, and this signal is detected using receiving antennas. Second, a wireless clock receiver with an integrated antenna detects a 15-GHz global clock signal supplied to an on-chip transmitting antenna located 5.6 mm away from the receiver, and generates a 1.875-GHz local clock signal. This is the first known demonstration of an on-chip clock transmitter with an integrated antenna and the second demonstration of a clock receiver with an integrated antenna, where the receiver's frequency and interconnection distance have approximately been doubled over previous results     

Optical True Time-Delay for Two-Dimensional X -Band Phased Array Antennas

An optical true time-delay (TTD) scheme for two-dimensional (2-D) X-band phased array antennas (PAAs) has been proposed. It is composed of a multiwavelength optical source and a delay line matrix consisting of 2times2 optical microelectromechanical system (MEMS) switches with fiber-optic delay lines connected between cross ports. A 2-bit times 4-bit optical TTD for 10-GHz 2-D PAAs has been implemented by cascading a wavelength-dependent TTD (WD-TTD) with a unit time delay of 12 ps in the x-direction and a wavelength-independent TTD (WI-TTD) with that of 6 ps in the y-direction. The time delay error for WD-TTD was measured to be less than 2.8 ps, mainly due to jitter incurred from gain-switching. On the other hand, the error for WI-TTD was less than 0.8 ps, which is within the equipment resolution. Insertion loss of both delay line matrices was less than 1 dB due to the column-wise control of the MEMS switches. This prevents the feed current applied to each antenna element from fluctuating at any radiation angles so that antenna gain and sidelobe level do not deteriorate in this scheme     

High-resolution multichannel pulse generator CMOS chip to drive ultrasonic array transducers

A multichannel pulser circuit, developed as an application specific integrated circuit (ASIC) in CMOS technology, is described. Each channel constitutes a programmable delay element of 1 ns time resolution. The chip is designed to drive linear or phased ultrasonic array transducers.<>     

激光测高仪中基于现场可编程门阵列的高精度飞行时间测量

设计了在激光测高系统中基于单芯片现场可编程门阵列(FPGA)的高精度时间间隔测量模块。该模块采用高频计数器实现粗时间测量,差分延时线内插技术完成细时间测量,时间分辨率为300 ps。该芯片同时还集成了时序切割电路、回波脉宽测量和数据传输模块等。在环境温度20℃时对该测量模块进行精度测试,获得标准偏差为94.68 ps,转换成距离为1.42 cm。最后通过地面检测,整个系统在500 km范围内的一般条件下可获得测高精度±50 cm。     

A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA

A fast-locking all-digital delay-locked loop(ADDLL) is proposed for the DDR SDRAM controller interface in a field programmable gate array(FPGA).The ADDLL performs a 90°phase-shift so that the data strobe(DQS) can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter(TDC) is proposed.A duty cycle corrector(DCC) is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13μm CMOS process,occupies a total of 0.017 mm~2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error(TIE) of the proposed circuit is 60.7 ps.     

An integrated high resolution CMOS timing generator based on anarray of delay locked loops

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with subgate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 μm CMOS process and an r.m.s. error of the time taps of 48 ps has been measured with a bin size of 0.15 ns. Used as a TDC device, an r.m.s. error of 76 ps has been obtained, A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives     

A high-resolution compact optical true-time delay beamformer using fiber Bragg grating and highly dispersive fiber

A high resolution optical true-time delay (OTTD) beamformer constructed by fiber Bragg grating (FBG) and highly dispersive fiber (HDF) is presented. It can produce the true time delay with the resolution of 1 ps. Besides the proposed system has compact structure and light weight even when a large number of antenna elements are present in a practical antenna array, this is because the used FBG fibers and HDFs are short and independent of the antenna element number. Theoretical analysis and numerical simulations are made. Proof-of-concept experiment results that demonstrate the feasibility of the system are presented.     

Precise delay generation using coupled oscillators

A new delay generator based on a series of coupled ring oscillators has been developed; it produces precise delays with subgate delay resolution for chip testing applications. It achieves a delay resolution equal to a buffer delay divided by the number of rings. The coupling employed forces the outputs of a linear array of ring oscillators oscillating at the same frequency to be uniformly offset in phase by a precise fraction of a buffer delay. The buffer stage used in the ring oscillators is based on a source-coupled pair and achieves high supply noise rejection while operating at low supply voltages. Experimental results from a 2-μm N-well CMOS implementation of the delay generator demonstrate that it can achieve an output delay resolution of 101 ps while operating at 141 MHz with a peak error of 58 ps     

Delay-locked loop technique for temperature stabilisation ofinternal delays of CMOS FPGA devices

A delay-locked loop (DLL) technique for use with typical CMOS field programmable gate array (FPGA) devices is presented. It allows for temperature stabilisation of the internal delays of the devices, especially when the digital delay lines are designed. The voltage V_cc supplying the FPGA device is varied within a limited range by the DLL to stabilise the internal delays of the device under changes in the ambient temperature. The method is illustrated by presenting results of the realisation of an interpolating time counter with 200 ps resolution, implemented on a single CMOS FPGA device     

A fully parallel CMOS analog median filter

A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on current saturating transconductance comparators, while the time delay is implemented using first-order all-pass filters. Both circuits allow modular expansion for the implementation of large median filter array processors. Based on these blocks, a new fast technique for parallel image processing is presented. It is shown that an image of 91/spl times/80 pixels can be processed in less than 8 /spl mu/s using an array of median filter cells. Experimental results of a test chip prototype in 2-/spl mu/m CMOS MOSIS technology are presented.     

Finite-difference time-domain analysis of integrated ceramic ball grid array package antenna for highly integrated wireless transceivers

This paper presents a study of the integration of an antenna in a ceramic ball grid array package for highly integrated wireless transceivers. The study has been carried out on an 11/spl times/11.66 mm/sup 2/ small microstrip antenna in a thin 48-ball ceramic ball grid array package with the finite-difference time-domain (FDTD) method in C band. The impedance and radiation characteristics of the antenna are examined. More importantly, the loading effects of the complementary metal-oxide-semiconductor (CMOS) chip and bond wires on the performance of the antenna are investigated. It is found that the loading generally increases the impedance bandwidth but decreases the radiation efficiency of the antenna. To minimize detrimental loading, the shield of the antenna from the CMOS chip is considered. A new design has been realized. The new antenna achieves impedance bandwidth of 4.65%, radiation efficiency of 63%, and gain of 5.6 dBi at 5.52 GHz.     

Fibre grating time delay element for phased array antennas

The authors have demonstrated an optical fibre grating based delay line which produces time delays in increments as small as 31 ps. The device could provide a true time delay component for a phased array antenna     

A low-power CMOS time-to-digital converter

A time-to-digital converter, TDC, with 780 ps lsb and 10-μs input range has been integrated in a 1.2-μm CMOS technology. The circuit is based on the interpolation time interval measurement principle and contains an amplitude regulated crystal oscillator, a counter, two pulse-shrinking delay lines, and a delay-locked loop for stabilization of the delay. The TDC is designed for a portable, low-power laser range-finding device. The supply voltage is 5±0.5 V, and the operating temperature range is -40 to +60°C. Single-shot accuracy is 3 ns and accuracy after averaging is ±120 ps with input time intervals 5-500 ns. In the total input range of 10 μs, the final accuracy after averaging is ±200 ps. Current consumption is 3 mA, and the chip size is 2.9 mm×2.5 mm     

A Single-Chip Ultra-Wideband Receiver With Silicon Integrated Antennas for Inter-Chip Wireless Interconnection

A single-chip ultra-wideband (UWB) receiver was developed using 0.18 mum CMOS technology, and inter-chip wireless data communication by integrated antennas was confirmed. Timing pulse and data pulse with on-off keying were alternately sent from a transmitting antenna. Double Gaussian monocycle pulse (GMP) template generators performed detections of timing and data pulses. A single GMP template, whose probability distribution of the pulse repetition cycle is given by Gaussian, showed a random jitter of 4.87 ps. Dual-Dirac model could explain the probability distribution of the cycle of double GMP template. Obtained random jitter and deterministic jitter were 4.6 ps and 14.4 ps, respectively. The receiver successfully recovered 200 Mbps data at the distance of 0.5 mm.     

相控阵雷达天线延时技术的发展

介绍了相控阵雷达天线在大扫描角及大瞬时带宽应用场景下延时补偿技术的发展概况。对天线阵列的波束色散现象以及延时补偿技术对天线方向图的影响进行了分析,并介绍了国内外的一些延时方案。依据延时实现架构,将其分为微波延时、表面声波延时、光延时以及数字延时四类。重点对微波延时的几种不同类型的实现形式进行了描述,并根据微波延时线实现载体的不同,分为GaAs 芯片、射频电缆、印制板和微同轴四种。另外,针对延时拓扑电路进行理论推导分析,说明单延时路径在电路设计上的优势,并分析了基态链路对延时路径的幅度、相位补偿和介质材料对延时量的误差引入。对相控阵雷达天线在大扫描角及大瞬时带宽应用场景下的延时补偿技术研究有一定参考价值。     

Monolithic Integration of a Folded Dipole Antenna With a 24-GHz Receiver in SiGe HBT Technology

The integration of an on-chip folded dipole antenna with a monolithic 24-GHz receiver manufactured in a 0.8-mum SiGe HBT process is presented. A high-resistivity silicon substrate (1000 Omega ldr cm) is used for the implemented circuit to improve the efficiency of the integrated antenna. Crosstalk between the antenna and spiral inductors is analyzed and isolation techniques are described. The receiver, including the receive and an optional transmit antenna, requires a chip area of 4.5 mm² and provides 30-dB conversion gain at 24 GHz with a power consumption of 960 mW.     

A V-band quasi-optical GaAs HEMT monolithic integrated antenna and receiver front end

A single-chip monolithic integrated V-band folded-slot antenna with two Schottky-barrier diodes and a local oscillator source is developed as a quasi-optical receiver for the first time. The monolithic microwave integrated circuit consists of a voltage-controlled oscillator (VCO), a coplanar waveguide (CPW)-to-slotline transition, a low-pass filter, a folded-slot antenna, and a 180/spl deg/ single balanced mixer. The chip is fabricated based on the 0.15-/spl mu/m GaAs high electron-mobility transistor technology and the overall chip size is 3/spl times/1.5 mm/sup 2/. A finite-difference time-domain method solver is also developed for analyzing the embedded impedance characteristics of the folded-slot antenna to design the mixer. The chip is placed on an extended hemispherical silicon substrate lens to be a quasi-optical receiver. The performance of the receiver is verified by experimental measurements. The VCO has achieved a tuning range from 61.9 to 62.5 GHz and approximately 9.3-dBm output power. The CPW-to-slotline transition has bandwidth from 50 to 70 GHz. The mixer results in 15-dB single-sideband conversion loss and the receiving patterns of the IF power are also measured.     

皮秒级精度可编程数模混合CMOS方波延时器

提出了一种基于数模混合CMOS电路的能实现皮秒级精度、线性化、延时时间、精度和范围可编程、能复制输入波形的小体积、低功耗、低成本及可单芯片化的方波延时器.分析了回路的工作原理,并利用Tanner EDA工具进行建模和仿真.结果表明采用0.6μm数模混合CMOS工艺,通过8位延时控制和2位范围选择信号,可实现最高约20ps/LSB的延时分辨率和最大约28ns的延时范围.