截尾卷积码的译码算法分析

介绍了截尾卷积码的循环维特比译码算法和BCJR译码算法，以及在循环维特比算法基础上改进的环绕维特比译码算法和双向维特比算法，最后对各种译码算法的性能进行了仿真分析。     

卷积码Viterbi译码器的硬件实现

第三代移动通信系统标准中普遍采用卷积码和Turbo码作为信道编码方案.本文首先阐述了维特比译码算法,然后论述了(2,1,3)卷积码编码电路和维特比译码的单片机实现方案.最后把维特比算法与交织方案相结合,统计结果表明纠错性能有较大改善.     

LTE系统中截尾卷积码译码算法研究及仿真性能分析

在LTE的下行控制信道和广播信道中采用了截尾卷积编码方式,本文介绍了LTE系统中采用的卷积编码器以及广播信道架构,详细分析了截尾卷积码的两种常用译码算法,文章提出了一种改进循环译码算法,在基于LTE-PBCH信道链路中对各种译码算法进行仿真,仿真测试结果表明,截尾卷积码可满足LTE信道对高速率业务的要求,双回溯循环译码算法的译码性能最佳。     

卷积译码的维特比算法和实现技术

介绍了卷积编码、解码的原理及适用于卷积码和网格码维特比译码的编程技术,叙述了用德州仪器(TI)TMS32054CX实现维特比算法的过程。认为此基本方法可用于对任何卷积码进行解码和译码,比如序列译码等。     

列表维特比译码算法在TD-SCDMA中的应用

卷积码在各通信系统中广泛使用,其最大似然(ML)译码算法为维特比译码算法(VA)。传统的维特比译码算法(CVA)仅产生一个最佳译码序列,在低信噪比(SNR)或者恶劣环境下,还是会出现较高概率的误判。为了提高译码性能,列表维特比算法(LVA)被提出,LVA可以同时产生L个候选最优幸存路径,对L个候选最优幸存路径分别进行校验比特验证,从而获得CVA更优的性能。在TD-SCDMA中大部分采用卷积编码的业务,文章将LVA应用到该系统中,并与CVA性能和实现复杂度上对比分析。从仿真结果可以看出,该LVA能提高1dB以上的性能增益。     

一种卷积码维特比译码算法的实现

卷积码编译码在现代数据通信中十分重要，对卷积码译码算法的研究也方兴未艾。本文在分析了卷积码译码的维特比译码算法后，给出了具体的实现方法。     

一种低复杂度咬尾卷积码译码算法﹡

对于咬尾卷积码的译码,传统的最大似然译码算法需要遍历每个可能的起始状态对应的咬尾格形子图,译码复杂度过高.循环维特比算法是一种有效的低复杂度次优译码算法.通过对循环维特比算法中的循环陷阱进行研究,提出了一种新的循环陷阱检测方法,利用对循环陷阱的检测可以减少冗余迭代;同时利用最大似然咬尾路径对非似然起始状态进行排除,极大的缩小了循环维特比算法中译码搜索空间.在此基础上得到了一种低复杂度的译码算法.     

一种约束卷积码的研究与仿真

通信系统中广泛使用的卷积码,其译码通常采用维特比译码的方法。为了获得更好的译码性能,在原有的卷积码的基础上提出一种约束卷积码算法。该约束卷积码是在发送系列中固定的位置加入确定的比特位,以在维特比译码时尽量获得发送序列的先验概率的基础上提高译码性能。通过对这种约束卷积码数学分析,提出其对应的编解码算法,并用蒙特卡罗仿真方法,验证该算法的正确性。     

Viterbi译码器的应用及其硬件设计与实现

维特比译码器是人们广泛采用的卷积码的译码器,在IS-95,GSM,3GPP中都有广泛的应用.文中首先简单说明Viterbi译码算法原理,接着分析Viterbi译码算法设计及伪代码实现,根据TD-SCDMA卷积码编码方案,设计了一种采用软判决方式的维特比译码器,并采用合理的归一化方式,保证了计算路径值的过程中不会发生溢出.仿真表明:改进的译码器具有良好的性能.     

卷积编译码盘的设计与实现

本文简要介绍了(2,1,3)卷积码的编译码设计与实现.编码电路可以用FPGA实现.译码采用维特比译码算法,应用高速数字信号处理器TMS320C50,实时完成高速处理任务,核心算法用软件实现.通过对算法进行分解优化,译码速度快.通过加载不同的译码软件可以在同一硬件平台上实现多种信道编译码算法.在工程中具有较高的应用价值和发展远景.     

低复杂度的TBCC自适应循环VA译码算法

咬尾是一种将卷积码转换为块码的技术,它消除了归零状态所造成的码率损失,同时避免了截尾带来的性能降低,在短块编码中具有明显优势.针对咬尾卷积码(TBCC)现有译码算法复杂度过大和收敛性问题,提出一种低复杂度的TBCC自适应循环维特比(VA)译码算法.该算法根据信道变化自适应调整译码迭代次数,使咬尾路径收敛到最佳.通过仿真...     

Two decoding algorithms for tailbiting codes

The paper presents two efficient Viterbi decoding-based suboptimal algorithms for tailbiting codes. The first algorithm, the wrap-around Viterbi algorithm (WAVA), falls into the circular decoding category. It processes the tailbiting trellis iteratively, explores the initial state of the transmitted sequence through continuous Viterbi decoding, and improves the decoding decision with iterations. A sufficient condition for the decision to be optimal is derived. For long tailbiting codes, the WAVA gives essentially optimal performance with about one round of Viterbi trial. For short- and medium-length tailbiting codes, simulations show that the WAVA achieves closer-to-optimum performance with fewer decoding stages compared with the other suboptimal circular decoding algorithms. The second algorithm, the bidirectional Viterbi algorithm (BVA), employs two wrap-around Viterbi decoders to process the tailbiting trellis from both ends in opposite directions. The surviving paths from the two decoders are combined to form composite paths once the decoders meet in the middle of the trellis. The composite paths at each stage thereafter serve as candidates for decision update. The bidirectional process improves the error performance and shortens the decoding latency of unidirectional decoding with additional storage and computation requirements. Simulation results show that both proposed algorithms effectively achieve practically optimum performance for tailbiting codes of any length.     

卷积码编码及其Viterbi译码算法的FPGA实现

探讨了卷积码编码及其Viterbi译码算法的FPGA（Field-Programmable GateArray）实现,根据编码器的结构,分别采用了有限状态机转换的编码法和基于流水线结构的状态转换译码法,有效地提高了编译码的速度.最后给出了（2,1,2）卷积码的编码及其Viterbi译码算法的实验仿真结果。     

An effective simplifying scheme for Viterbi decoder

A Viterbi decoding algorithm with a scarce-state transition-type circuit configuration, namely the probability selecting states (PSS) mode decoder, is presented. The algorithm has reduced complexity compared to a conventional Viterbi decoder. It is shown that this method has three advantages over the general Viterbi algorithm: it is suitable to the quick look-in code, it applies the optimum decoding in a PSS-type decoder, and it makes full use of the likelihood concentration property. The bit-error-rate (BER) performance of a r=1/2, k=7 (147,135) code and PSS-type Viterbi decoder approximates the optimum performance of the standard Viterbi decoder and reduces the hardware of the conventional Viterbi decoder to about half     

The Choice of the Desired Impulse Response in Combined Linear-Viterbi Algorithm Equalizers

Equalizer structures using the Viterbi Algorithm achieve at least order of magnitude performance improvement over linear equalizers on some intersymbol interference channels. Using a linear equalizer to shape the original channel impulse response to some shorter desired impulse response (DIR) is a technique which reduces the complexity of the Viterbi Algorithm equalizer. This paper looks at three techniques for choosing a DIR. These are choosing the DIR by truncation, minimum mean square error and matching the power spectrum to that of the original channel. Using effective signal to noise ratio as the figure of merit for comparison, results are given for one particular channel.     

短波3G-ALE系统物理层关键技术研究

3G-ALE系统中的0号突发波形(BW0)用于链路建立,对整个系统起到关键作用。通过对3G-ALE系统同步捕获、解扩、译码等关键技术的研究,提出了一种针对BW0的改进接收方案,该方案融合了正交解扩比特软值提取算法、Rake接收技术、环绕Viterbi译码算法(WAVA)等技术,并仿真了高斯白噪声信道及多径衰落信道下的性能。仿真结果表明,在各种信道条件下,与现有工作相比,在相同的信噪比下改进的接收方案有更高的建连概率。     

A constraint-length based modified Viterbi algorithm with adaptiveeffort

A modified Viterbi (1971) algorithm for convolutional codes is described that provides for signal-to-noise ratio (SNR) adaptive computational effort. The algorithm has three levels of prioritized effort. Movement from one level to the next is controlled by parameters that can be selected according to desired output bit error rate performance. For 3-bit soft decision detected signals, a coding gain within 0.06 dB of Viterbi at a 3-dB SNR is achieved for the same constraint-length code with modest parameter values and computational effort. At values of SNR above 6 dB, the algorithm decodes with very low computational effort. Effort levels are controlled by spanning the decoding trellis in steps that are one constraint-length long     

A Multiple Stack Algorithm for Erasurefree Decoding of Convolutional Codes

A new algorithm for erasurefree sequential decoding of convolutional codes is introduced which achieves low error probabilities at substantially higher decoding speeds than the Viterbi decoding algorithm. The algorithmic properties of the Multiple Stack Algorithm (MSA) are investigated and it is demonstrated that the MSA reaches a decision with an exponentially rather than Pareto distributed computational effort. The MSA's error probability on the binary symmetric channel is studied as a function of its parameters and its performance and complexity compared to that of the Viterbi algorithm. The MSA is seen to achieve equal and lower error probabilities with a significantly lower average decoding effort. The new algorithm can thus be considered an attractive alternative to the Viterbi algorithm where low error probabilities and high decoding speeds are required simultaneously.     

Soft-Output BEAST Decoding With Application to Product Codes

A Bidirectional Efficient Algorithm for Searching code Trees (BEAST) is proposed for efficient soft-output decoding of block codes and concatenated block codes. BEAST operates on trees corresponding to the minimal trellis of a block code and finds a list of the most probable codewords. The complexity of the BEAST search is significantly lower than the complexity of trellis-based algorithms, such as the Viterbi algorithm and its list generalizations. The outputs of BEAST, a list of best codewords and their metrics, are used to obtain approximate a posteriori probabilities (APPs) of the transmitted symbols, yielding a soft-input soft-output (SISO) symbol decoder referred to as the BEAST-APP decoder. This decoder is employed as a component decoder in iterative schemes for decoding of product and incomplete product codes. Its performance and convergence behavior are investigated using extrinsic information transfer (EXIT) charts and compared to existing decoding schemes. It is shown that the BEAST-APP decoder achieves performances close to the Bahl–Cocke–Jelinek–Raviv (BCJR) decoder with a substantially lower computational complexity.