A low-power 2.4-GHz transmitter/receiver CMOS IC

A 2.4-GHz CMOS receiver/transmitter incorporates circuit stacking and noninvasive baseband filtering to achieve a high sensitivity with low power dissipation. Using a single 1.6-GHz local oscillator, the transceiver employs two upconversion and downconversion stages while providing on-chip image rejection filtering. Realized in a 0.25-/spl mu/m digital CMOS technology, the receiver exhibits a noise figure of 6 dB and consumes 17.5 mW from a 2.5-V supply, and the transmitter delivers an output power of 0 dBm with a power consumption of 16 mW.     

A 123-mW W-CDMA uplink baseband receiver IC with beamforming capability

In this paper, architecture and circuit design of a beamforming baseband receiver IC for uplink W-CDMA communication systems is presented. In the proposed receiver, a four-antenna-element beamformer and a four-finger RAKE combiner are adopted to exploit both spatial diversity and path diversity receiving. To minimize the size and power consumption of the receiver, a latch-based 1024-tap complex delay line is custom designed for the matched filter in the channel estimation circuit. The receiver chip was fabricated in a 0.35-/spl mu/m n-well CMOS single-poly quadruple-metal technology. The minimum supply voltage with the chip running at the nominal 15.36-MHz clock rate is measured at 2.15 V. The chip has an area of 6 mm by 6.3 mm and a power consumption of about 123 mW.     

A software-defined communications baseband design

Software-defined radios offer a programmable and dynamically reconfigurable method of reusing hardware to implement the physical layer processing of multiple communications systems. An SDR can dynamically change protocols and update communications systems over the air as a service provider allows. In this article we discuss a baseband solution for an SDR system and describe a 2 Mb/s WCDMA design with GSM/GPRS and 802.11b capability that executes all physical layer processing completely in software. We describe the WCDMA communications protocols with a focus on latency reduction and unique implementation techniques. We also describe the underlying technology that enables software execution. Our solution is programmed in C and executed on a multithreaded processor in real time.     

A baseband processor for impulse ultra-wideband communications

This paper presents a baseband processor architecture for pulsed ultra-wideband signals. It consists of an analog-to-digital converter (ADC), a clock generation system, and a digital back-end. The clock generation system provides different phases of a 300-MHz clock using four differential inverter stages. The specification of the jitter standard deviation is 100 ps. The Flash interleaved ADC provides four bit samples at 1.2 Gsps. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 65 /spl mu/s. The entire synchronization algorithm is implemented in the digital domain, without feeding any signals back to the clock control. The baseband processor and ADC were implemented on the same 0.18-/spl mu/m CMOS die at 1.8 V as part of a complete baseband transceiver. A wireless data rate of 193 kb/s is demonstrated.     

A two-sensor array blind beamformer for direct sequence spreadspectrum communications

We present an efficient blind beamformer dedicated to the problem of interference mitigation in direct sequence spread spectrum (DSSS) communication systems using a two-sensor array. A closed-form solution for the blind identification of the communication channel is derived by exploiting the temporal properties of the desired signal and the interference. The optimal beamformer is derived from the maximization of the signal-to-interference and noise ratio (SINR) at the output of the receiver in terms of the blindly estimated channel coefficients. Three structures of the DSSS receiver are presented. One structure consists of the blind beamformer followed by the spread spectrum demodulator. The other two structures consist of the spread spectrum demodulator followed by the blind beamformer. The performance of these structures is discussed in terms of the achieved SINR and the computational cost. Simulation results are provided to illustrate the effectiveness of the proposed blind beamformers in interference excision     

A low-power transponder IC for high-performance identificationsystems

A novel CMOS integrated circuit for a batteryless transponder system is presented. Batteryless transponders require contactless transmission of both the information and power between a mobile data carrier and a stationary or handheld reader unit. The operating principle of this system gives a superior performance in reading distance due to separation of the powering and data transmission phases-compared to systems with continuous powering and damping modulation. This paper describes the function of the transponder IC and the circuit design techniques used for the various building blocks     

A postdistortion receiver for mobile communications

The paper presents a postdistortion receiver, for possible future mobile communication systems, which can potentially increase both the spectral efficiency and the transmitter's power efficiency (especially important for portable units). Postdistortion is a technique, implemented at the base-station receiver, to compensate for AM-AM and AM-PM nonlinearities of a mobile transmitter's amplifier which, if uncompensated, would cause adjacent channel interference. A unique adaptation method is demonstrated to compensate for slow variations in the power amplifier's characteristics without an interruption for a training period. Various aspects of system performances, including SNR and convergence speed, have been simulated. The system performance in fading channel conditions is also considered. The simulation and measured results show that the postdistortion technique can improve the out-of-band emission by up to 20 dB; the corresponding increase in mobile transmitter power efficiency is approximately a factor of 10. The spectral efficiency is approximately increased by 20% with the postdistortion implementation     

A low-power all-digital FSK receiver for space applications

A frequency-shift keying (FSK) receiver has been designed for deep space applications which exhibits potential for ultra low power performance. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler. The architecture utilizes subsampling and 1-bit data processing together with a discrete Fourier transform-based detection scheme to enable power consumption dramatically lower than implementations reported in the literature. Novel and power-efficient algorithms are derived for frequency and timing tracking. Most of the power saving techniques are applicable to a variety of applications, but some are achieved by taking advantage of the asymmetric power constraints for the receiver and the transmitter as well as the absence of adjacent channel interferers. The worst-case bit-error rate (BER) performance of the receiver is just 2.5 dB below that of the optimal uncoded noncoherent FSK receiver at a BER of 10^-6 and better for lower BERs     

A flexible receiver for CDMA multiuser communications

Code division multiple access (CDMA) capacity is limited by interference amongst users. The effect of this interference on receiver outputs depends on the users' signatures and the actual detector used in the receiver. A matched filter receiver is particularly sensitive to interference, whereas an optimum multiuser receiver is less sensitive but infeasible due to its exponential complexity. We propose a receiver structure that trades detection performance for reduced complexity. It can interpolate between the performances and complexities of these two receivers. Our detector uses a tree structure, and some of its special cases are the decision feedback detector, the decorrelating detector, and the optimal linear detector. We show that at equal complexity levels, a particular implementation of our detector outperforms these detectors. We also show that our approach can be used with a minimum-mean-square-error design criterion and coded CDMA transmission     

A low-power multirate differential PSK receiver for space applications

Wireless communication for deep-space and satellite applications needs to accommodate the Doppler shift caused by the movement of the space vehicle and should consume low power to conserve the onboard power. A low-power phase-shift keying (PSK) receiver has been designed for such applications. The receiver employs double differential detection to be robust against Doppler shift and uses subsampling with a 1-bit A/D converter and digital decimation architecture at the front end to achieve low-power consumption. The receiver is also designed to be programmable to operate using single-stage differential detection instead of double-stage differential detection at low Doppler rates to obtain optimum performance. Furthermore, the baseband can be employed in either direct subsampling or intermediate frequency (IF)-sampling front ends. Both front ends offer minimal power consumption and differ from traditional types by replacing some conventional analog components such as a voltage-controlled oscillator, mixer, or phase-locked loop with their digital counterparts. This eliminates problems due to dc offset, dc voltage drifts, and low-frequency (LF) noise. The paper also includes a brief discussion of the nonidealities existing in real applications. The proposed phase shift keying (PSK) receiver supports a wide range of data rates from 0.1-100 Kbps and has been implemented in a CMOS process.     

A high performance baseband transceiver for SISO-/MIMO-OFDA uplink communications

In this paper, a single-input single-output-/multipleinput multiple-output- (SISO-/MIMO-) OFDMA uplink baseband transceiver based on IEEE 802.16e-2005 is proposed. To compensate for the interference of carrier frequency offset (CFO), an inter-carrier interference-based (ICI-cancellationbased) CFO estimator in conjunction with channel estimation and MIMO detector is proposed. Moreover, a low complexity solution for implementation is also provided. Simulation results show that the mean-square-error (MSE) performance of the proposed CFO estimator can be reduced to about one tenth compared to other methods and the bit-error-rate (BER) performance of the proposed transceiver is quite close to that of an ideal system that doesn?t include CFO compensation.     

A direct-conversion receiver IC for WCDMA mobile systems

A prototype design of a 2.7-3.3-V 14.5-mA SiGe direct-conversion receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a bypassable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the receiver IC is characterized using a software baseband processor to compute link bit-error rate.     

A voltage overscaled low-power digital filter IC

In this brief, we present an integrated circuit implementation of a low-power digital filter in 0.35-/spl mu/m 3.3-V CMOS process. The low-power technique combines voltage overscaling (VOS) and algorithmic noise tolerance (ANT) to push the limits of energy efficiency beyond that achievable by voltage scaling alone. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40%-67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1-dB loss in SNR for a wide range of filter bandwidths (0.05f/sub s/-0.25f/sub s/, where f/sub s/ is the sampling frequency).     

PPM调制的超宽带差分接收机

提出一种PPM-DIFF-UWB调制方式及其接收机,该接收机采用三条具有不同延时特性的相关支路实现PPM-UWB信号的差分接收,提供了一种关于PPM调制的超宽带信号的低复杂度的接收方式,可用于实现在密集多径信道下的多径分集接收,且不需要复杂的信道估计以及发送额外的参考信号.理论分析和实验仿真结果表明该接收机的误码性能优于常规的PPM-TR-UWB接收机.     

A novel turbo GFDM-IM receiver for MIMO communications

Generalized frequency-division multiplexing (GFDM) is a candidate waveform for the fifth generation (5G) wireless communication systems. However, the carrier frequency offset (CFO) causing synchronization problem is very important for GFDM system. In this paper, we propose a turbo receiver with channel estimation, equalization and CFO compensation for MIMO (multiple input multiple output) GFDM system with index modulation (IM). So far, no related researches exist. This paper proposes a novel receiver to solve CFO compensation with two-path transmission and proposes a modified phase rotated conjugate cancellation (PRCC) algorithm for the receiver. On the other hand, GFDM with index modulation (GFDM-IM) can achieve better performance and lower peak-to-average power ratio (PAPR) than those of GFDM by using active index subcarrier. To reduce the system complexity, the log-likelihood ratio (LLR) criteria is also employed to search which subcarrier is active. Moreover, the Kalman filter is employed to trace the time-varying channels. The initial channel estimation is performed by the sparse pilot signals. In the simulations, we compare the proposed receiver with several existing schemes in different time-varying channels and modulations. The proposed scheme outperforms the existing schemes.     

A new blind receiver for downlink DS-CDMA communications

A linear receiver is proposed for downlink DS-CDMA communications over unknown frequency-selective fading channels. The new receiver exploits the fact that all synchronized downlink signals go through the same channel and recovers the desired signal with a constrained channel equalizer followed by a despreader. Such a scheme allows the receiver to operate blindly in a time varying environment for both periodic CDMA and aperiodic CDMA systems     

A low-power highly digitized receiver for 2.4-GHz-band GFSK applications

This paper describes the design and measurement results of a low-power highly digitized receiver for Gaussian frequency-shift keying modulated input signals at 2.4 GHz. The RF front-end has been based on a low-IF architecture and does not require any variable gain or filtering blocks. The full dynamic range of the low-IF signal is converted into the digital domain by a low-power high-resolution time-continuous SigmaDelta analog-to-digital converter (ADC). This leads to a linear receive chain without limiters. A fifth-order poly-phase loop filter is used in the complex SigmaDelta ADC. The digital block performs filtering and demodulation. Channel filtering is combined with matched filtering and the suppression of noise resulting from the SigmaDelta ADC. The high degree of digitization leads to design flexibility with respect to changing standards and scalability in future CMOS generations. The receiver has been realized in a standard 0.18-mum CMOS process and measures 3.5 mm². The only external components are an antenna filter and a crystal. The power consumption is only 32 mW in the continuous mode, which is at least a factor of two lower than state-of-the-art CMOS receivers     

A low-power 200-MHz receiver for wireless hearing aid devices

The design of a low-power receiver for a wireless hearing aid system working in the 174-223-MHz range and its implementation in a 0.8-/spl mu/m BiCMOS technology is shown. The chip comprises a low-noise amplifier, an RF mixer, a variable-gain IF amplifier, and a demodulator. The latter consists of a digital phase shifter and I/Q IF mixers, fifth-order Bessel filters, and dc amplifiers. Measurements demonstrate that merely 667 /spl mu/A is consumed for the reception of an 8-ary phase-shift keying signal with a data rate of 336 kb/s. The receiver works with different modulation formats, including those carrying information in the amplitude.     

A low-power CMOS super-regenerative receiver at 1 GHz

A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35-μm CMOS process is described. The receiver includes a low-noise amplifier, a super-regenerative oscillator, an envelope detector, an AGC circuit with sample/hold function, and a baseband amplifier. The die surface is equal to 0.25 mm ². The power consumption is less than 1.2 mW at V_DD=1.5 V. A 100-kHz sawtooth quench signal is used to achieve a rejection of -36 dB at 500 KHz from the central frequency     

A low-power, low-cost bipolar GPS receiver chip

A low-power, low-cost, integrated global positioning by satellite (GPS) receiver is described. It operates from a single 2.7-5.5 V supply with a nominal current consumption of only 27 mA. Furthermore, there is no need for expensive external surface acoustic wave (SAW) filters or a radio frequency voltage-controlled oscillator (VCO) module; only a low frequency reference clock (temperature compensated crystal oscillator (TCXO) or crystal), varactor diodes and standard passive elements are necessary for full operation. The chip is compatible with baseband chips requiring 1 fo (1.023 MHz) and 4 fo signal frequencies. The device has been integrated using a 15-GHz silicon bipolar technology