A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm/sup 2/

A 12-bit 320-MSample/s current-steering D/A converter in 0.18-/spl mu/m CMOS is presented. In order to achieve high linearity and spurious free dynamic range (SFDR), a large degree of segmentation has been used, with the seven most significant bits (MSBs) being implemented as equally weighted current sources. A "design-for-layout" approach has allowed this to be done in an area of just 0.44 mm/sup 2/. The increased switching noise associated with a high degree of segmentation has been reduced by a new latch architecture. Differential nonlinearity of /spl plusmn/0.3 LSB and integral nonlinearity of /spl plusmn/0.4 LSB have been measured. Low-frequency SFDR of 95 dB has been achieved, while SFDR at 320 MS/s remains above 70 and 60 dB for input frequencies up to 10 and 60 MHz, respectively. The converter consumes a total of 82 mW from 1.8-V and 3.3-V supplies. The validity of the techniques used has been demonstrated by fabricating the converter in two separate 0.18-/spl mu/m processes with similar results measured for both.     

Analog characterization of low-voltage MQW traveling-wave electroabsorption modulators

In this paper, high-speed traveling-wave electroabsorption modulators (TW-EAMs) with strain-compensated InGaAsP multiple quantum wells as the absorption region for analog optical links have been developed. A record-high slope efficiency of 4/V, which is equivalent to a Mach-Zehnder modulator with a V/sub /spl pi// of 0.37 V and a high extinction ratio of > 30 dB/V have been measured. A detailed study of the nonlinearity and the spurious-free dynamic range (SFDR) is presented. By optimizing the bias voltage and the input optical power, the SFDR can be improved by 10-30 dB. After minimizing the third-order distortion, an SFDR as high as 128 dB-Hz/sup 4/5/ is achieved at 10 GHz. A simple link measurement was made using this EAM and an erbium-doped fiber amplifier and a 50-/spl Omega/ terminated photodetector. At 10 GHz, a link gain of 1 dB is achieved at a detected photocurrent of 7.6 mA with higher gains at lower frequencies. The dependence of link gains on bias voltage, input optical, and radio frequency powers are investigated in detail.     

Peripheral-coupled-waveguide MQW electroabsorption modulator for near transparency and high spurious free dynamic range RF fiber-optic link

Peripheral coupled waveguide (PCW) design has been deployed in InGaAsP multiple quantum-well (MQW) electroabsorption modulator (EAM) at 1.55-/spl mu/m wavelength. PCW enhances the optical saturation power and reduces the optical insertion loss and the equivalent V/sub /spl pi// simultaneously. A radio-frequency link using a 1.3-mm-long lumped-element PCW EAM has achieved experimentally a link gain of -3 dB, at 500 MHz and at input optical power of 80 mW. The corresponding two-tone multioctave spurious-free dynamic range (SFDR) at the same bias is measured at 118 dB/spl middot/Hz/sup 2/3/. The single-octave SFDR at the third-order null bias is 132 dB/spl middot/Hz/sup 4/5/.     

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.     

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.     

Analog performance of an ultrafast sampled-time all-optical fiber XPM wavelength converter

Analog performance of an all-optical ultrafast wavelength converter is measured and reported for the first time. The wavelength-conversion process is based on nonlinear cross-phase modulation in an optical fiber combined with an optical filter to convert phase modulation to amplitude modulation. The spurious-free dynamic range (SFDR) of the converter is measured to be 82 dB/spl middot/Hz/sup 2/3/. We define a new metric called the SFDR power penalty, which measures the degradation in SFDR relative to baseline the back-to-back analog optical link. The SFDR power penalty was measured to be 5 dB/spl middot/Hz/sup 2/3/ and is shown to be a function of the input optical power. This metric is used to characterize the linear region of the optical wavelength converter.     

A 10-bit 250-MS/s binary-weighted current-steering DAC

This paper studies the impact of segmentation on current-steering digital-to-analog converters (DACs). Segmentation may be used to improve the dynamic behavior of the converter but comes at a cost. A method for reducing the segmentation degree is given. The presented chip, a 10-bit binary-weighted current-steering DAC, has >60 dB SFDR at 250 MS/s from DC to Nyquist. At 62.5 MHz signal frequency and 250 MS/s, we operated the device in 9-bit unary, 1-bit binary-weighted mode. The obtained 60 dB SFDR in this measurement demonstrates that the binary nature of the converter did not limit the SFDR. The chip draws 4 mW from a dual 1.5 V/1.8 V supply plus load currents. The active area is less than 0.35 mm/sup 2/ in a standard 1P-5M 0.18-/spl mu/m 1.8-V CMOS process. Both INL and DNL are below 0.1 LSB.     

An embedded 0.8 V/480 /spl mu/W 6b/22 MHz flash ADC in 0.13-/spl mu/m digital CMOS process using a nonlinear double interpolation technique

For high-data-rate wireless communication, low-voltage baseband converters integrated with DSP in deep submicrometer processes are area- and power-efficient. Through careful architecture selections and circuit techniques, this paper demonstrates a low-voltage (0.8 V), low-power (480 /spl mu/W), 6-b/22-MHz flash-interpolation ADC which occupies 0.3 mm/sup 2/ and achieves 33 dB SNDR and 47 dB SFDR. The power efficiency of this converter is 0.6 pJ/conv-step which compares favorably with all published results. We also introduce a nonlinear double interpolation technique that enables the use of a 0.13-/spl mu/m standard digital CMOS process without special resistors.     

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digital-to-analog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signal-to-noise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a low-latency, segmented, dynamic element-matching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the first-stage residue amplifier to settle. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process and has a die size of 4mm/spl times/5 mm.     

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

A new power reduction technique for analog-to-digital converters (ADCs) is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-poly 7-metal CMOS technology. The 10-bit ADC dissipates 55 mW from 1.2-V supply, when the ADC operates at 200 mega-samples per second (MSPS). The 10-bit, 200-MSPS ADCs achieve maximum differential nonlinearity (DNL) of 0.66 least significant bit (LSB), maximum integral nonlinearity (INL) of 1.00 LSB, a spurious-free dynamic range (SFDR) of 66.5 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 54.4 dB that corresponds to 8.7 effective number of bits (ENOB). The active area is 1.8 mm /spl times/ 1.4 mm.     

A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2

A 10-b current steering CMOS digital-to-analog converter (DAC) is described, with optimized performance for frequency domain applications. For sampling frequencies up to 200 MSample/s, the spurious free dynamic range (SFDR) is better than 60 dB for signals from DC to Nyquist. For sampling frequencies up to 400 MSample/s, the SFDR is better than 55 dB for signals from DC to Nyquist. The measured differential nonlinearity and integral nonlinearity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively. The circuit is fabricated in a 0.35-μm, single-poly, four-metal, 3.3 V, standard digital CMOS process and occupies 0.6 mm². When operating at 500 MSample/s, it dissipates 125 mW from a 3.3 V power supply. This DAC is optimized for embedded applications with large amounts of digital circuitry     

一种数字CMOS工艺制造的10位100MS/s流水线ADC

介绍了采用0.18μm数字工艺制造、工作在3.3V下、10位100MS/s转换速率的流水线模数转换器。提出了一种适用于1.5位MDAC的新的金属电容结构,并且使用了高带宽低功耗运算放大器、对称自举开关和体切换的PMOS开关来提高电路性能。芯片已经通过流片验证,版图面积为1.35mm×0.99mm,功耗为175mW。14.7MS/s转换速率下测得的DNL和INL分别为0.2LSB和0.45LSB,100MS/s转换速率下测得的DNL和INL分别为1LSB和2.7LSB,SINAD为49.4dB,SFDR为66.8dB。     

A 64-MHz clock-rate /spl Sigma//spl Delta/ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.     

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than ±0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-μm CMOS technology and has an active area of only 0.35 mm²     

A 2-GS/s 3-bit /spl Delta//spl Sigma/-modulated DAC with tunable bandpass mismatch shaping

Direct digital synthesis of signals in the hundreds of megahertz can lead to simpler, smaller transceivers, free of images and LO feedthrough that plague systems requiring analog upconversion. We present a 3-bit, 2 GS/s, /spl Delta//spl Sigma/-modulated DAC in InP HBT technology. The DAC is linearized using bandpass mismatch shaping. The mismatch shaper uses seven tunable 1.5-bit discrete-time bandpass /spl Delta//spl Sigma/ modulators to dynamically route the digital signals to the DACs. These /spl Delta//spl Sigma/ modulators operate in the analog domain to decrease system complexity and power consumption. The mismatch-shaped DAC can generate narrowband signals between 250-750 MHz with >68 dB SNR in a 1-MHz bw, >74-dB SFDR, and <-80-dBc intermodulation distortion with an 8.1-W power consumption.     

A 1.3-V 5-mW fully integrated tunable bandpass filter at 2.1 GHz in 0.35-/spl mu/m CMOS

A 2.1-GHz 1.3-V 5-mW fully integrated Q-enhancement LC bandpass biquad programmable in f/sub o/, Q, and peak gain is implemented in 0.35-/spl mu/m standard CMOS technology. The filter uses a resonator built with spiral inductors and inversion-mode pMOS capacitors that provide frequency tuning. The Q tuning is through an adjustable negative-conductance generator, whereas the peak gain is tuned through an input G/sub m/ stage. Noise and nonlinearity analyses presented demonstrate the design tradeoffs involved. Measured frequency tuning range around 2.1 GHz is 13%. Spiral inductors with Q/sub o/ of 2 at 2.1 GHz limit the spurious-free dynamic range (SFDR) at 31-34 dB within the frequency tuning range. Measurements show that the peak gain can be tuned within a range of around two octaves. The filter sinks 4 mA from a 1.3-V supply providing a Q of 40 at 2.19 GHz with a 1-dB compression point dynamic range of 35 dB. The circuit operates with supply voltages ranging from 1.2 to 3 V. The silicon area is 0.1 mm/sup 2/.     

Characterization of the jitter in a mode-locked Er-fiber laser and its application in photonic sampling for analog-to-digital conversion at 10 gsample/s

This paper compares two approaches for evaluating the amplitude and timing jitters of an Er-fiber laser mode-locked at 10 GHz. Using a low-noise oscillator as the clock drive for the mode-locking, relative amplitude jitter was measured as low as 0.0384% and timing jitter as low as 0.0153% (/spl Delta/f=100 Hz-40 MHz). Applying the mode-locked pulse train in a photonic sampling experiment at 10 Gsample/s, a spurious free dynamic range (SFDR) of /spl sim/48.5 dB (over the Nyquist bandwidth of 5 GHz) for multiple analog inputs at L band (1-2.6 GHz). These results correspond to an analog-to-digital conversion resolution of /spl sim/8 SFDR bits at 10 Gsample/s. Finally, the use of "instantaneous companding" is demonstrated to correct for third-order distortions generated by a Mach-Zehnder modulator used in the photonic sampling link.     

A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

This paper presents a prototype analog-to-digital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closed-loop gain errors, closed-loop gain variation, and slew-rate limiting. The prototype consists of an input sample-and-hold amplifier (SHA) that can serve as a calibration queue, a 12-bit 80-MSample/s pipelined ADC, a digital-to-analog converter (DAC) for calibration, and an embedded custom microprocessor, which carries out the calibration algorithm. The calibration is bootstrapped in the sense that the DAC is used to calibrate the ADC, and the ADC is used to calibrate the DAC. With foreground calibration, test results show that the peak differential nonlinearity (DNL) is -0.09 least significant bits (LSB), and the peak integral nonlinearity (INL) is -0.24LSB. Also, the maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 71.0 and 79.6dB with a 40-MHz sinusoidal input, respectively. The prototype occupies 22.6 mm/sup 2/ in a 0.25-/spl mu/m CMOS technology and dissipates 755 mW from a 2.5-V supply.     

A direct digital frequency synthesizer with fourth-order phase domain /spl Delta//spl Sigma/ noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage /spl Delta//spl Sigma/ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q/sup 2/ Random Walk switching scheme. The /spl Delta//spl Sigma/ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage /spl Delta//spl Sigma/ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-/spl mu/m CMOS technology with active area of 1.11mm/sup 2/ including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm/sup 2/. The total power consumption of the DDFS is 200mW with a 3.3-V power supply.     

A 14-bit delta-sigma ADC with 8/spl times/ OSR and 4-MHz conversion bandwidth in a 0.18-/spl mu/m CMOS process

A 14-bit 8/spl times/ oversampling delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter (ADC) for wide-band communication applications has been developed. By using a novel architecture, a high maximum out-of-band quantization noise gain (Q/sub max/) is realized, which greatly improves the SNR and tonal behavior. The ADC employs a fifth-order single-stage structure with a 4-bit quantizer. It achieves 82-dB SNDR and 103-dB SFDR at 4-MHz conversion bandwidth with a single 1.8-V power supply.