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由于非结构化的低密度奇偶校验码(LDPC)具有更优异的纠错性能而受到广泛关注,但其非零元素分布较不规律且没有循环或准循环的子矩阵的构造方式,增加了译码器实现的设计难度.本文提出了基于CUDA的译码器设计,用于支持任意非结构化LDPC码的高吞吐量并行译码.利用校验矩阵压缩重排、优化信息存储等手段,设计实现GPU上高效的并... 相似文献
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普通准循环低密度校验码(QC-LDPC)按照SHIFT结构特性分层时,层内并行度难以提高。提出了一种非均匀抽取分层方法,可在保证层内行(列)重至多为1的前提下,提高层内并行度,并设计了相应的寻址结构和流水结构,进而提高吞吐率。对于实际应用中的2种标准码型——空间数据系统咨询委员会(CCSDS)深空通信(5 632,4 096)码和中国地面数字电视传输(DTMB)标准(7 493,6 096)码,层内并行度对比均匀抽取分别提升41.3%和32.2%。对深空通信码的综合结果表明,对比采用均匀抽取的译码器,使用双相消息传递译码算法时,可在相同资源利用率的情况下提高吞吐率41.3%;使用按列分层译码算法时,译码系统最大吞吐率可提升28.2%。 相似文献
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针对部分并行结构的准循环低密度校验(QC-LDPC)码译码器,提出了一种将译码准码字存储在信道信息和外信息存储块中的高效存储方法,该方法不需要额外的存储块来存储译码准码字,能够减少译码器实验所需的存储资源数量,并且有效降低了译码电路的布线复杂度.在Xilinx XC2V6000-5ff1152 FPGA上的实验结果表明,提出的QC-LDPC码译码器设计方法能够在降低系统的BRAM资源需求量的同时有效地提高系统的运行频率和译码吞吐量. 相似文献
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针对具有准循环结构的LDPC码,设计了一种低复杂度译码器。利用校验矩阵的循环特性以及分层迭代的译码算法,对一般的分层迭代架构进行改进,实现了译码器流水线处理,有效的减少迭代时间,提高吞吐量,最后针对码长为1200的LDPC码,基于FPGA平台Kintex7 xc7k325的芯片实现了该架构设计,结果表明,该译码器只消耗了100多个Slices和几块RAM,有效节省了硬件资源,同时译码时间比一般的分层架构减少了2/3左右,吞吐量提高了约2倍,研究成果具有重要的实用价值,可应用于资源有限的低速通信领域。 相似文献
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以(8 176,7 154)准循环码为研究对象,介绍了准循环低密度奇偶校验(LDPC)码及其译码算法,分析了译码器的硬件结构单元,并详细介绍了各个分块单元。在Xilinx公司的硬件上仿真实现了所设计的译码器,并在平台上对其进行测试。仿真结果表明所设计的高速译码器编码效率为7/8,吞吐量达到600 Mbps,在高速数数据传输系统中具有重大的工程应用价值。 相似文献
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In this paper we present a Base-matrix based decoder architecture for multi-rate QC-LDPC codes proposed in broadband broadcasting system. We use the Modified Min-Sum Algorithm (MMSA) as the decoding algorithm in this architecture, which lowers the complexity of the LDPC decoder while keeping almost the same performance or even better. Based on this algorithm, we designed a novel check node processing unit to reduce the complexity of the decoder and facilitate the multiplex of the processing units. The decoder designed with hardware constraints is not only scalable in throughput, but also easily configurable to support different QC-LDPC codes flexible in code rate and code length. 相似文献
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Wang Z. Cui Z. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(1):104-114
This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations 相似文献
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Wang Z. Cui Z. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(4):483-488
This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems 相似文献
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针对QC-LDPC码的Tanner图中存在的短环,尤其是4环,对迭代译码性能产生不利影响的问题,寻找到一种有限域乘群构造法,该方法构造的QC-LDPC码的Tanner图中不存在任何4环。基于此方法构造的码长为3 060,码率为的(3,12)规则QC-LDPC码,选用Altera公司StratixII系列的EP2S60F484C4器件,对其实现了分层译码器硬件结构的设计。实现结果表明,在最大迭代次数为5时,时钟频率最高可达35.38 MHz,吞吐量达到92.27 Mbit·s-1。 相似文献
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This paper presents an efficient memory-address remapping technique for a high-throughput quasi-cyclic low-density parity check (QC-LDPC) decoder. In general, an LDPC decoder needs a large size of embedded memories for the temporal storage of the check node process (CNP) and variable node process (VNP) outputs. To increase the decoder throughput, overlapping the CNP and VNP operations is necessary; however, the parallel operations are mainly restricted by the embedded memory bandwidth. This work presents an efficient memory management approach in an LDPC decoder, where the memory-address conflicts and redundant memory-read operations are effectively reduced by using a proposed memory-address remapping technique. As a result, parallel variable node unit operations significantly increase, leading to higher throughput. When the proposed approach is applied to the various code rates of IEEE std. 802.16-2009, increases in decoding speed of up to 1.52X per iteration are achieved for overlapped message passing algorithm-based architecture, along with considerable reductions in the number of memory-read accesses. Using a 0.13- \(\upmu \) m CMOS process, a QC-LDPC decoder with multi-code rates is implemented, and the experimental results show that the proposed decoder achieves considerable throughput area ratio increase with energy savings compared to the conventional approaches. 相似文献
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《Microelectronics Journal》2014,45(11):1489-1498
In this paper, an area efficient and high throughput multi-rate quasi-cyclic low-density parity-check (QC-LDPC) decoder for IEEE 802.11n applications is proposed. An overlapped message passing scheme and the non-uniform quantization scheme are incorporated to reduce the overall area and power of the proposed QC-LDPC decoder. In order to enhance the decoding throughput and reduce the size of memories storing soft messages, an improved early termination (ET) scheme and base matrix reordering technique is employed. These techniques significantly reduce the total number of decoding iterations and memory accessing conflicts without mitigating the decoding performance. Equipped with these techniques an area efficient and high throughput multi-rate QC-LDPC decoder is designed, simulated and implemented with Xilinx Virtex6 (XC6VLX760-2FF1760) for an irregular LDPC code of length 1944 and code rates (1/2–5/6) specified in IEEE 802.11n standard. With a maximum clock frequency of 574.136–587.458 MHz the proposed QC-LDPC decoder can achieve throughput in the range of 1.27–2.17 Gb/s for 10 decoding iterations. Furthermore, by using Cadence RTL compiler with UMC 130 nm VLSI technology, the core area of the proposed QC-LDPC decoder is found to be 1.42 mm2 with a power dissipation in the range of 101.25–140.42 mW at 1.2 V supply voltage. 相似文献
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Yongmei Dai Zhiyuan Yan Ning Chen 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(5):565-578
Efficient hardware implementation of low-density parity-check (LDPC) codes is of great interest since LDPC codes are being considered for a wide range of applications. Recently, overlapped message passing (OMP) decoding has been proposed to improve the throughput and hardware utilization efficiency (HUE) of decoder architectures for LDPC codes. In this paper, we first study the scheduling for the OMP decoding of LDPC codes, and show that maximizing the throughput gain amounts to minimizing the intra- and inter-iteration waiting times. We then focus on the OMP decoding of quasi-cyclic (QC) LDPC codes. We propose a partly parallel OMP decoder architecture and implement it using FPGA. For any QC LDPC code, our OMP decoder achieves the maximum throughput gain and HUE due to overlapping, hence has higher throughput and HUE than previously proposed OMP decoders while maintaining the same hardware requirements. We also show that the maximum throughput gain and HUE achieved by our OMP decoder are ultimately determined by the given code. Thus, we propose a coset-based construction method, which results in QC LDPC codes that allow our optimal OMP decoder to achieve higher throughput and HUE. 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(4):582-587
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针对不可分层LDPC码无法采用分层译码算法的问题,设计了一种新型的LDPC码分层译码器。与传统分层译码器的结构不同,新结构在各层间进行并行更新,各层内进行串行更新。通过保证在不同分层的同一变量节点不同时进行更新,达到分层译码算法分层递进更新的目标。选用Altera公司的CycloneⅢ系列EP3C120器件,实现码率3/4,码长8 192的(3,12)规则不可分层QC-LDPC码译码器的布局布线,在最大迭代次数为5次时,最高时钟频率可以达到45.44 MHz,吞吐量可以达到47.6 Mbps。 相似文献
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Random linear network coding is an efficient technique for disseminating information in networks, but it is highly susceptible to errors. Kötter-Kschischang (KK) codes and Mahdavifar-Vardy (MV) codes are two important families of subspace codes that provide error control in noncoherent random linear network coding. List decoding has been used to decode MV codes beyond half distance. Existing hardware implementations of the rank metric decoder for KK codes suffer from limited throughput, long latency and high area complexity. The interpolation-based list decoding algorithm for MV codes still has high computational complexity, and its feasibility for hardware implementations has not been investigated. In this paper we propose efficient decoder architectures for both KK and MV codes and present their hardware implementations. Two serial architectures are proposed for KK and MV codes, respectively. An unfolded decoder architecture, which offers high throughput, is also proposed for KK codes. The synthesis results show that the proposed architectures for KK codes are much more efficient than rank metric decoder architectures, and demonstrate that the proposed decoder architecture for MV codes is affordable. 相似文献