基于FPGA的SDRAM控制器设计

SDRAM是一种大容量、高速度的动态存储器，在电子设计领域应用很广泛。本文介绍了在雷达光栅显示系统中，应用SDRAM作为视频存储器时，采用FPGA实现控制电路的过程．     

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells.If we want to reduce the overall power in the memory system,we have to work on the input circuitry of memory architecture i.e.row and column decoder.In this research work,low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed.In this work,the comparison of cluster DECODER,body bias DECODER,source bias DECODER,and source coupling DECODER are designed and analyzed for memory array application.Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool.Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92％ and static energy by 99.92％ at a supply voltage of 1.2 V.The proposed circuit also improves dynamic power dissipation by 5.69％,dynamic PDP/EDP 65.03％ and delay 57.25％ at 1.2 V supply voltage.     

Concurrent fault simulation on message passing multicomputers

Even though hardware accelerators are common in very large scale integration (VLSI) computer-aided design (CAD), fault simulation is a notable exception because of limited availability of memory, the need for dynamic memory management and the complexity of the algorithms themselves. Although simplified fault simulation algorithms that assume a zero delay circuit model can be accelerated, their applicability is limited. Most application specific integrated circuits (ASIC's) designed in industry today have on-chip memory blocks of different dimensions and characteristics, enhancing the complexity of a fault simulator. In this paper, we present a multiple delay algorithm for concurrent fault simulation of logic gates and functional memory blocks. This algorithm has been implemented on the microprogrammable accelerator for rapid simulation (MARS) hardware accelerator system with a 22 MHz clock and a capacity to simulate circuits with millions of devices. Speedup factors of 20 to 30 are easily achieved when compared to software simulators running on comparable hardware platforms and using identical circuit models     

High-density static ESFI MOS memory cells

The area of static MOS memory cells is reduced by avoiding crossovers in the flip-flop, and by selecting the cell by a diode. Such cells have been realized in epitaxial silicon films on insulators (ESFI) with complementary transistors, diodes, and high-rated load resistors; the cell areas can be as small as 1500 /spl mu/m/SUP 2/ (2.4 mil/SUP 2/), and are the smallest areas of static MOS memory cells known so far. The static and dynamic behavior of these cells are discussed, as well as their behavior in a large-scale integrated (LSI) circuit; for this purpose an exploratory memory with 4096 bits and with simple decoding and sensing circuitry has been realized on an area of 3.5/spl times/4.2 mm (140/spl times/170 mils). Taking into account the measured data, an ESFI MOS memory circuit shows a better performance in speed and power dissipation than dynamic MOS memories, but its principal advantage is the static operation mode.     

A new extension method of retention time for memory cell on dynamic random access memory

Demands have been placed on dynamic random access memory (DRAM) to not only increase memory capacity and data transfer speed but also to reduce operating and standby currents. When a system uses DRAM, the restricted data retention time necessitates a refresh operation because each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to memory capacity. A new method is proposed to reduce the refresh power consumption dynamically, when full memory capacity is not required, by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation of retention times among memory cells. The proposed method reduces the frequency of disturbance and power consumption by two orders of magnitude. Furthermore, the conversion itself can be realized very simply from the structure of the DRAM array circuit, while maintaining all conventional functions and operations in the full array access mode.     

基于AES加密电路的防复制电路及系统设计

随着各种抄板技术和芯片解剖技术的发展,嵌入式系统芯片正面临着越来越多受攻击风险,如何保护嵌入式系统产品不受非法复制,正日益受到人们的关注,各种防复制方法也应运而生。由此设计了一款软硬件协同的新型防复制电路及系统,用以实现对嵌入式软件版权的保护。防复制电路采用AES加密算法与嵌入式芯片进行多次随机动态加密验证,使破解者无法通过监控通信数据来破解验证保护。防复制电路中内置CPU和安全存储器,用来存储关键数据以及执行部分嵌入式程序,让破解者无法获得嵌入式芯片中完整的程序,从软硬件两方面实现了对嵌入式产品版权的充分保护。本电路在FPGA上进行了实现,并搭建被保护芯片与防复制FPGA电路的联合保护系统,实测结果显示该系统很好的完成了防复制的功能,未通过动态加密验证无法启动系统,此外,没有防复制电路的配合,无法执行完整的嵌入式芯片中的程序。     

GaAs/AlGaAs dynamic random access memory cell

A single-transistor dynamic random access memory circuit using a GaAs/AlGaAs structure as the storage cell and modulation-doped field-effect transistors for memory accessing and output sensing has been developed. The functionality of the memory is demonstrated and a storage time of 5.4s is measured at room temperature.<>     

多隧道结单电子动态存储器的Monte Carlo模拟

本文采用Monte Carlo方法模拟了多隧道结单电子动态存储器的存储特性，考察了隧道结的个数、隧道结电容、隧道结电阻、脉冲电压幅度等参数对存储器的存储时间和饱和充电电荷的影响，并与宏观RC电路进行了比较。     

A Composite Circuit Model for NDR Devices in Random Access Memory Cells

Devices exhibiting negative differential resistance (NDR), such as resonant tunneling diodes and Esaki-type diodes, offer the promise of converting a dynamic random access memory (DRAM) cell to operate like a static random access memory cell with potentially lower dynamic power dissipation and faster read and write operations than a conventional DRAM. However, a circuit model that describes the operation of the resulting novel memory cell and is of use for both hand analysis and design, and circuit simulation as has yet been developed due to the non-analytical current-voltage curve of the two NDR devices in the cell. In this paper, a "composite" circuit model is presented that describes the relationship between current and voltage at the common node of connection of the two NDR devices. The composite model is analytical and can easily be implemented in SPICE or any circuit simulator. It is also useful for hand analysis of the read/write performance metrics. Finally, comparisons of composite models are presented     

Changes in the level of the permanent potential of the deep brain structures in rabbits with a Brown-Pearce carcinoma

Rabbits with the Brown-Pierce carcinoma have been studied in chronic experiments for dynamics of the permanent potential reflecting bioelectrochemical processes in different structures of the hypothalamic and limbic system: medial preoptic area, ventromedial nucleus, posterior hypothalamic area, basal and lateral amygdalas, hippocampus, nucleus coeruleus as well as in central nucleus of the suture. The space-temporal pattern of neurodynamic changes in the subcortical brain structures has been found. These changes correlated with developmental characteristics of the Brown-Pierce carcinoma.     

A new CR-delay circuit technology for high-density and high-speedDRAMs

The capacitance-resistance (CR) delay circuit technology assures full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions and thus realizes a fast access time. A noise compensation scheme is used to generate a constant delay even under the power supply line noise. The circuit was applied to a 4 Mbit dynamic RAM (DRAM) peripheral circuit. As a result, timing loss as well as malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time, compared with a conventional design using normal inverter chains, have been achieved     

CS8831CN测试方法

CS8 8 31CN是用于语音录放的单片CMOSLSI,采用ADM (自适应增量调制 )。它与动态RAM以及包括话筒、扬声器、放大器等的音频电路共同构成一个完整的语音录放系统。     

Negative resistance element for a static memory cell based onenhanced surface generation [MOS devices]

A negative resistance (NR) element for a static memory cell using enhanced surface generation of MOS devices is proposed. Such a memory cell will maintain information with extremely small current information and the control circuitry can be the same as in one-transistor dynamic memories. The mechanism of operation is discussed and some experimental data are presented. It is shown that in order to maintain information in a single static memory cell, the required current can be as low as a few picoamperes. Operating currents are large enough to compensate for leakage currents of storage capacitors in dynamic RAM (DRAM) memories. By adding the proposed circuit in parallel with those capacitors, the dynamic memory can be converted into a static memory requiring no refresh circuit or restoring circuit. In the proposed memory structure, the storage capacitor can be reduced significantly or perhaps even eliminated. This will result in much faster operation in comparison to DRAM memories     

Behaviour of Lyapunov’s function for different strategies of circuit optimisation

The process of analogue circuit optimisation is mathematically defined as a controllable dynamic system. In this context the minimisation of the processor time of designing can be formulated as a problem of time minimisation for transitional process of dynamic system. In order to analyse the properties of such a system, it is proposed to use the concept of Lyapunov function of dynamic system. Using this function and its time derivative, the special functions have been built that allow us to predict the total processor time for circuit optimisation by analysing the initial interval of the optimisation process. Numerical results indicate the possibility of predicting the processor time of different strategies for circuit optimisation.     

Dynamic depletion mode: an E/D MOSFET circuit method for improved performance

A new method of designing enhancement/depletion (E/D) MOSFET circuits, involving the dynamic or pulsed use of depletion-mode devices, is described. The method can result in improvements in performance and/or power in the design of memory, logic, and driver circuits. The method is compared with the standard approach to the design of E/D circuits. Several circuits designed by the method have been simulated by use of a numerical circuit analysis program and have been placed on an experimental test chip. Theoretical and experimental results are presented.     

Design of a New Chaos Circuit and Its Encryption to Digital Information

With the development of Internet and multimedia technology, multimedia communication has become the most important method to transmit information. Meanwhile, the problem of information security is more important than ever [1, 2]. In resent years, applying chaos dynamic systems to information encryption has caused great interesting to many authors. The study in this field has developed a new aspect, chaotic cryptography. It has advantages of simple algorithms, key sequence generated easily, se…     

一种低功耗异步FIFO存储器的设计

针对传统异步FIFO功耗较高的缺点,设计一种低功耗异步FIFO存储器。通过采用对异步读写指针的前两个状态位直接比较的方法,减少格雷码向二进制转换的电路,并增加门控时钟电路,从而大大降低了存储器的动态功耗。通过软件QuartusⅡ7.2对其进行功耗估算,功耗降低了8%。用ModelSim SE 6.1b进行仿真,验证了设计功能的正确性。     

A content addressable memory using Josephson junctions

A content-addressable memory circuit using Josephson nondestructive readout (NDRO) memory cells is described. The memory circuit proposed performs searching functions, such as coincidence, incoincidence, and don't-care functions, in addition to the conventional memory function of writing and reading. This memory circuit is able to achieve the `less than' function in addition to the three functions listed above. Computer simulation of a 3-word by 3-b memory was used to investigate how high-performance operation can be achieved. The simulation results show that the four operations for all combinations of binary inputs have been achieved with a cycle time of less than 80 ps and a 0.28-μW/cell dissipation. The simulation results also show the design tolerances of the gate currents of four superconducting quantum interference device (SQUID) gates used in the memory circuit to range from 25% to 17%     

A 64K/spl times/1 bit dynamic ED-MOS RAM

A 64K/spl times/1 bit dynamic RAM based on an innovative short channel ED-MOS process technology and an improved ED-MOS sense amplifier circuit has been realized. The RAM has been designed by using 2-3 /spl mu/m design rules and employing ED-MOS peripheral circuits capable of low supply voltage operation. As a result, dynamic memory operation has been demonstrated with an access time less than 140 ns and a cycle time of 350 ns, using a single 5 V power supply.     

A 2.5D Ferrite Memory Sense Amplifier

In recent years, large-core memories have been developed that use two-wire arrays and are operated in a mode colloquially called 2.5D. The intrinsic noise problem in a 2.5D ferrite memory system is quite severe because the core signals must be sensed off an array line which is also conducting a half-select drive current. The resulting large pedestal and delta noise components, which are generated during the read cycle, severely limit the memory performance. While the delta noise can be strobed out of the sense amplifier, the pedestal noise must be eliminated by circuit techniques. To handle this noise problem, a delay and difference amplification technique is used that permits a short recovery from the pedestal noise and a corresponding increase in memory speed. The implementation of this circuit function is shown, in the final analysis, to be a relatively simple filter used in conjunction with a conventional difference amplifier and detector.