嵌入式系统软件体系结构设计

本文采用嵌入式实时系统软件设计方法对星载姿轨控计算机系统进行设计，软件系统采用层次模块化结构。采用嵌入式实时操作系统连接姿轨控应用程序和底层硬件，文中给出了姿轨控计算机软件系统设计流程图、软件应用层纵横结合型结构，以及任务模块调度管理的仿真结果。     

图像信息处理机嵌入实时系统软件设计方法

介绍了图像信息处理机的应用需求和特定的硬件结构,以该处理机实时操作系统和实时应用软件的设计方法为例,探讨了在强实多、多处理机系统中一种先进的设计方法－DARTS方法的设计思想和步骤。     

A Real-Time Scheduler Design for a Class of Embedded Systems

We consider here the design aspect of a real-time scheduler for a class of embedded systems. For this purpose, we design a feedback controller for a reservation-based CPU scheduler for soft real-time systems. The execution time of soft real-time systems, such as multimedia systems, portable MP3 players, personal digital assistants, cellular phones, and embedded Web servers is highly variable. Hence, it is crucial to assign an adequate amount of CPU resources for the running tasks to guarantee the quality of service. On the other hand, it is also important not to allocate the large amount of resources to avoid waste. The purpose of this paper is to attain the aforementioned crucial objectives for a class of embedded systems under real-time computing constraints. Specifically, we provide an analytical model for a real-time scheduler in terms of a switched system with time-varying uncertainty. Moreover, by using Lyapunov stability in a linear matrix inequalities (LMIs) framework, we design a state feedback controller that stabilizes the switched system. This, in fact, achieves the regulation of scheduling errors caused by time-varying uncertainty to a desired level. We extend an LMI-framework-based control scheme to a relatively new control application domain, i.e., a soft realtime scheduling domain. We provide performance analysis under scheduler simulation environments and implement a feedback bandwidth server scheduler under a real-time kernel simulator. In the simulation studies, the advantages of the controller design scheme are clearly highlighted in comparison with some conventional existing open-loop systems.     

Hardware-Software Partitioning for Real-Time Embedded Systems

In this paper, we present an approach to hardware-software partitioning for real-time embedded systems. Hardware and software components are modeled at the system level, so that cost and performance tradeoffs can be studied early in the design process and a large design space can be explored. Feasibility factor is introduced to measure the possibility of a real-time system being feasible, and is used as both a constraint and an attribute during the optimization process. An imprecise value function is employed to model the tradeoffs among multiple performance attributes. Optimal partitioning is achieved through the use of an existing computer-aided design tool. We demonstrate the application of our approach through the design of an example embedded system.     

Hardware/Software Design Considerations for Automotive Embedded Systems

An increasing number of safety-critical functions is taken over by embedded systems in today's automobiles. While standard microcontrollers are the dominant hardware platform in these systems, the decreasing costs of new devices as field programmable gate arrays (FPGAs) make it interesting to consider them for automotive applications. In this paper, a comparison of microcontrollers and FPGAs with respect to safety and reliability properties is presented. For this comparison, hardware fault handling was considered as well as software fault handling. Own empirical evaluations in the area of software fault handling identified advantages of FPGAs with respect to the encapsulation of real-time functions. On the other hand, several dependent failures were detected in versions developed independently on microcontrollers and FPGAs.      

Multi-Valued Performance Metrics for Real-Time Embedded Systems

To rapidly explore the design space of a real-time embedded system, it is essential to be able to efficiently analyze the timing behaviors of different system architectures. This includes not only determining if a design can satisfy all the timing constraints but also comparing the timing performance of different designs for tradeoff purposes. Understanding the exact timing behavior of a large system can be computationally prohibitive. Previous work in this area has mostly focused on producing a yes/no answer to the schedulability of a system architecture under the worst-case scenario. This not only often leads to overly pessimistic designs, but also provides no insight as how to rank different architectural designs with respect to their timing performance. In this paper, we present several metrics that may be used to measure the timing performance of a design. The metrics were analyzed using workloads from both real-world task systems and randomly generated task systems. A superior metric has been identified through analysis of large sets of experiments. We also show, through an example, how this metric can be used effectively during a design exploration process.     

嵌入式移动系统GIS的引擎开发

许多嵌入式移动系统能够运用GIS图形在终端设备上显示对象的空间位置.基于GIS的移动系统如果利用比较通用的GIS引擎来开发可以节约时间、降低成本、方便维护.GIS引擎支持不同的地理管辖区域,支持不同类型移动终端,提供必要的工具,支持基于GIS应用的的通用功能.GIS点阵图格元模型、屏幕显示域的定义、屏幕显示域的移动算法及GIS图形自动适应不同类型终端屏幕是实现GIS引擎的重要技术.     

Real-Time Adaptive Background Modeling for Multicore Embedded Systems

Current trends in microprocessor design integrate several autonomous processing cores onto the same die. These multicore architectures are particularly well-suited for computer vision applications, where it is typical to perform the same set of operations repeatedly over large datasets. These memory- and computation-intensive applications can reap tremendous performance and accuracy benefits from concurrent execution on multi-core processors. However, cost-sensitive embedded platforms place real-time performance and efficiency demands on techniques to accomplish this task. Furthermore, parallelization and partitioning techniques that allow the application to fully leverage the processing capabilities of each computing core are required for multi-core embedded vision systems. In this paper, we evaluate background modeling techniques on a multicore embedded platform, since this process dominates the execution and storage costs of common video analysis workloads. We introduce a new adaptive backgrounding technique, multimodal mean, which balances accuracy, performance, and efficiency to meet embedded system requirements. Our evaluation compares several pixel-level background modeling techniques in terms of their computation and storage requirements, and functional accuracy for three representative video sequences, across a range of processing and parallelization configurations. We show that the multimodal mean algorithm delivers comparable accuracy of the best alternative (Mixture of Gaussians) with a 3.4× improvement in execution time and a 50% reduction in required storage for optimal block processing on each core. In our analysis of several processing and parallelization configurations, we show how this algorithm can be optimized for embedded multicore performance, resulting in a 25% performance improvement over the baseline processing method.     

USB嵌入式系统上层应用软件的设计与实现

系统在USB协议基础上，以DVD解决方案为依托，实现嵌入式USB主机系统在家庭娱乐消费产品中的应用软件设计与实现。文章介绍了USB协议的相关内容，系统结构的设计，系统部分上层软件的设计。     

Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems

In this paper, we combine coarse-grained software pipelining with DVS (Dynamic Voltage/Frequency Scaling) for optimizing energy consumption of stream-based multimedia applications on multi-core embedded systems. By exploiting the potential of multi-core architecture and the characteristic of streaming applications, we propose a two-phase approach to solve the energy minimization problem for periodic dependent tasks on multi-core processors with discrete voltage levels. With our approach, in the first phase, we propose a coarse-grained task-level software pipelining algorithm called RDAG to transform the periodic dependent tasks into a set of independent tasks based on the retiming technique (Leiserson and Saxe, Algorithmica 6:5–35, 1991). In the second phase, we propose two DVS scheduling algorithms for energy minimization. For single-core processors, we propose a pseudo-polynomial algorithm based on dynamic programming that can achieve optimal solution. For multi-core processors, we propose a novel scheduling algorithm called SpringS which works like a spring and can effectively reduce energy consumption by iteratively adjusting task scheduling and voltage selection. We conduct experiments with a set of benchmarks from E3S (Dick 2008) and TGFF () based on the power model of the AMD Mobile Athlon4 DVS processor. The experimental results show that our technique can achieve 12.7% energy saving compared with the algorithms in Zhang et al. (2002) on average.

Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems

In this brief, we propose a novel real-time loop-scheduling technique to minimize energy consumption via dynamic voltage scaling (DVS) for applications with loops considering transition overhead. One algorithm, dynamic voltage loop scheduling (DVLS), is designed integrating with DVS. In DVLS, we repeatedly regroup a loop based on rotation scheduling and decrease the energy by DVS as much as possible within a timing constraint. We conduct the experiments on a set of digital signal processing benchmarks. The experimental results show that DVLS achieves big energy saving compared with the traditional time-performance-oriented scheduling algorithm     

用Linux实时系统设计飞机电子水平状态指示仪软件

针对液晶式电子水平状态指示仪应用时图形显示速度慢的问题,提出基于嵌入式Linux实时系统的软件设计方案。给出软件设计原则、设计思路和消息机制,并详细分析贴图、Linux下进程间通信和多级缓冲等关键技术。对软件运行结果进行分析,软件在帧速率和CPU使用率方面均能达到较好效果,能够满足设计需求。该方案有效提高了电子水平状态指示仪界面显示速度和质量。     

The One-Shot Task Model for Robust Real-Time Embedded Control Systems

Embedded control systems are often implemented in small microprocessors enabled with real-time technology. In this context, control laws are often designed according to discrete-time control systems theory and implemented as hard real-time periodic tasks. Standard discrete-time control theory mandates to periodically sample (input) and actuate (output). Depending on how input/output (I/O) operations are performed within the hard real-time periodic task, different control task models can be distinguished. However, existing task models present important drawbacks. They generate task executions prone to violate the periodic control demands, a problem known as sampling and latency jitter, or they impose synchronized I/O operations at each task job execution that produce a constant but artificially long I/O latency.      

环绕智能系统中移动终端软件设计与实现

本文讨论了环绕智能实现的技术,以及在环绕智能平台上移动终端(PDA与智能手机)软件的设计与实现方法.这种实现使环绕智能控制器能在特定的物理空间中进行多用户的身份实时感知,并为用户提供个性化、智能化的服务.     

EPON系统ONU嵌入式软件设计

本文EPON系统的嵌入式软件设计采用主从模式构建．ONU侧利用面向对象的开发方法和共享存储的组织方式实现了嵌入式软件的代码可重用和资源易维护的特性。0NU嵌入式软件中硬件抽象层的设计提高了0NU嵌入式软件的可移植性．ONU自动加入和多任务间通信的实现方式满足了ONU嵌入式软件对稳定性、可靠性和实时性的要求。     

软硬件联合管理实时嵌入式多媒体应用

随着嵌入式处理解决方案复杂性和普及度的提高,软件工程师发现需要将多媒体算法从基于PC系统(带有足够大存储器)的概念验证移植到嵌入式系统,而资源管理对满足性能要求是非常必要的.理想情况下,他们希望在不增加其"舒适"的编程模式的复杂程度情况下,获得尽可能好的性能.图1描述了软件工程师们在功耗、存储器分配和性能方面面临的挑战.     

The REAR Framework for Emulation and Analysis of Embedded Hard Real-Time Systems

The aim of rapid prototyping real-time applications is to substantially reduce development times by confirming the functional and temporal requirements of the application at a very early stage of development with the help of an executable prototype. Hence, the real-time rapid prototyping system presented in this paper integrates two complementary tasks: On one hand it provides an automated design environment for a rapid and facile generation of a working prototype. On the other hand, the design process is extended with real-time requirement specification and analysis in order to prove that the embedded system will meet all timing requirements, and to verify that the timing requirements have been modeled correctly. The REAR framework uses annotated SDL for the system specification, from which both, the compilable source codes and the real-time analysis model are generated. After instrumentation for timing measurements, the C and VHDL source code is compiled and synthesized, linked with communication libraries and executed on the configurable, heterogeneous multiprocessor target system. Several case studies demonstrate the feasibility of this approach.     

计算机软件设计中嵌入式实时软件的运用分析

随着计算机软件设计的发展,嵌入式实时软件得到充分的利用,提高了软件在计算机中的使用水平,最主要的是简化软件的设计流程。嵌入式实时软件在软件设计中的发展前景比较好,优化了计算机软件的运行环境,有助于消除软件设计中的缺陷。因此,文章通过对嵌入式实时软件进行研究,分析具体的实践运用。