一种基于负载选择的光分组交换缓存结构

提出了一种基于业务负载选择的光分组交换(OPS)网络的光缓存结构,根据业务负载大小灵活选择缓存方式。输出缓存光纤延迟线(FDL)采用分段式共享机制配置,输出/反馈共享缓存模块采用简并式配置,以提高有限数目FDL的利用率。分析和仿真表明,这种可选择的缓存结构可以有效降低丢包率和OPS节点需求的FDL数目。     

High-speed buffer management for 40 gb/s-based photonic packet switches

We develop a method of high-speed buffer management for output-buffered photonic packet switches. The use of optical fiber delay lines is a promising solution to constructing optical buffers. The buffer manager determines packet delays in the fiber delay line buffer before the packets arrive at the buffer. We propose a buffer management method based on a parallel and pipeline processing architecture consisting of (log/sub 2/N+1) pipeline stages, where N is the number of ports of the packet switch. This is an expansion of a simple sequential scheduling used to determine the delays of arriving packets. Since the time complexity of each processor in the pipeline stages is O(1), the throughput of this buffer management is N times larger than that of the sequential scheduling method. This method can be used for buffer management of asynchronously arriving variable-length packets. We show the feasibility of a buffer manager supporting 128 /spl times/ 40 Gb/s photonic packet switches, which provide at least eight times as much throughput as the latest electronic IP routers. The proposed method for asynchronous packets overestimates the buffer occupancy to enable parallel processing. We show through simulation experiments that the degradation in the performance of the method resulting from this overestimation is quite acceptable.     

Blocking and Delay Analysis of Single Wavelength Optical Buffer With General Packet Size Distribution

Buffers are essential components of any packet switch for resolving contentions among arriving packets. Currently, optical buffers are composed of fiber delay lines (FDL), whose blocking and delay behavior differ drastically from that of conventional RAM at least two-fold: 1) only multiples of discrete time delays can be offered to arriving packets; 2) a packet must be dropped if the maximum delay provided by optical buffer is not sufficient to avoid contention, this property is called balking. As a result, optical buffers only have finite time resolution, which may lead to excess load and prolong the packet delay. In this paper, a novel queueing model of optical buffer is proposed, and the closed-form expressions of blocking probability and mean delay are derived to explore the tradeoff between buffer performance and system parameters, such as the length of the optical buffer, the time granularity of FDLs, and to evaluate the overall impact of packet length distribution on the buffer performance.     

A Necessary and Sufficient Condition for the Construction of 2-to-1 Optical FIFO Multiplexers by a Single Crossbar Switch and Fiber Delay Lines

In this paper, we prove a necessary and sufficient condition for the construction of 2-to-1 optical buffered first-in-first-out (FIFO) multiplexers by a single crossbar switch and fiber delay lines. We consider a feedback system consisting of an (M+2)times(M+2) crossbar switch and M fiber delay lines with delays d₁,d₂,...,d_M. These M fiber delay lines are connected from M outputs of the crossbar switch back to M inputs of the switch, leaving two inputs (respectively, two outputs) of the switch for the two inputs (respectively, two outputs) of the 2-to-1 multiplexer. The main contribution of this paper is the formal proof that d₁=1 and d_i les d_i+1 les 2d _i, i=1,2,...,M-1, is a necessary and sufficient condition on the delays d₁,d₂,...,d_M for such a feedback system to be operated as a 2-to-1 FIFO multiplexer with buffer Sigma_i=1 ^Md_i under a simple packet routing policy. Specifically, the routing of a packet is according to a specific decomposition of the packet delay, called the C- transform in this paper. Our result shows that under such a feedback architecture a 2-to-1 FIFO multiplexer can be constructed with M=O(log B), where B is the buffer size. Therefore, our construction improves on a more complicated construction recently proposed by Sarwate and Anantharam that requires M=O(radicB) under the same feedback architecture (we note that their design is more general and works for priority queues)     

On the design of asynchronous optical packet switch architectures with shared delay lines and converters

Optical packet switching (OPS) is a promising technology to enable next-generation high-speed IP networks. A major issue in OPS is packet contention that occurs when two or more packets attempt to access the same output fiber. In such a case, packets may be dropped, leading to degraded overall switching performance. Several contention resolution techniques have been investigated in the literature including the use of fiber delay lines (FDLs), wavelength converters (WCs), and deflection routing. These solution typically induce extra complexity to the switch design. Accordingly, a key design objective for OPS is to reduce packet loss without increasing switching complexity and delay. In this paper, we investigate the performance of contention resolution in asynchronous OPS architectures with shared FDLs and WCs in terms of packet loss and average switching delay. In particular, an enhanced FDL-based and a novel Hybrid architecture with shared FLDs and WCs are proposed, and their packet scheduling algorithms are presented and evaluated. Extensive simulation studies show that the performance of proposed FDL-based architecture outperforms typical OPS architectures reported in the literature. In addition, it shown that, for the same packet loss ratio, the proposed hybrid architecture can achieve up to 30% reduction in the total number of ports and around 80% reduction in the overall length of fiber as compared to the FDL-based architectures.     

Fiber-Optic Switch Based on Fiber Bragg Gratings

This letter presents a design proposal of optical packet switch architecture which incorporates fiber Bragg gratings (FBGs) and fiber delay line (FDL) to resolve contention among packets. The main feature of the architecture is the efficient use of FBG to create the buffer and there is no requirement of demux and splitter inside the buffer as in most of the conventional optical packet switch (OPS) architectures. Thus, the buffer is simplified in terms of required number of components used to create buffer. The FBG inside the buffer is a new approach towards buffering structure. Finally, comparative study of the proposed architecture with other architectures is presented.      

An effective buffering architecture for optical packet switching networks

A novel optical buffering architecture for Optical Packet Switching (OPS) networks is proposed in this article. The architecture which adopts a fiber-sharing mechanism aims at solving the problem of using a large number of fiber delay lines that are used to solve resource contention in the core node in OPS networks. The new architecture employs fewer fiber delay lines compared to other simple architectures, but can achieve the same performance. Simulation results and analysis show that the new architecture can decrease packet loss probability effectively and achieve reasonable performance in average packet delay.

基于同波长光纤延迟线集光突发交换结构及其性能分析

由于光突发交换机制本身就避免了光缓存的使用，但是现实中，光突发包之间竞争以及提供优先级服务又依靠光纤延迟线来解决。为此，我们设计了应用光纤延迟线的光突发交换网络核心节点结构。为了避免光纤延迟线色散引起的突发包输入排队缓存偏移，在该结构中设计了同波长光纤延迟线集。采用了空分交换矩阵，避免了波长转换的需要。为了有效运行该交换结构，我们提出了输入排队与自适应光缓存调度算法，而该算法不仅仅适用于光突发交换，也适合于光纤延迟线得到普遍应用的光分组交换。该调度算法能够提供优先级服务，避免队头阻塞，对该调度算法建立了严格的理论分析模型，并进行了仿真。仿真结果表明，与传统的延迟线竞争解决方案相比，这一调度算法能够改善交换性能1到2个数量级，是利用光纤延迟线解决光突发交换中竞争问题的一个较佳方案。     

异步光分组交换的缓存排序方案及性能

分析了简单的先到先服务(FCFS)光纤延迟线(FDL)循环占用方案性能,发现其分组丢失率(PLR)较高,提出3种输入分组按长度排序,寻找最小的FDL缓存优化分配方案.分析和仿真结果表明:约10%的分组排序后使3种方案都大大地能减小PLR,最小长度分组占用最小可用FDL缓存方案的性能最好.业务负载低于0.8时,排序的缓存方案对管理有限的FDL是有效的.     

Scheduling Algorithms for a Slotted Packet Switch with either Fixed or Variable Length Packets

We address the problem of congestion resolution in optical packet switching (OPS). We consider a fairly generic all-optical packet switch architecture with a feedback optical buffer constituted of fiber delay lines (FDL). Two alternatives of switching granularity are addressed for a switch operating in a slotted transfer mode: switching at the slot level (i.e., fixed length packets of a single slot) or at the burst level (variable length packets that are integer multiples of the slot length). For both cases, we show that in spite of the limited queuing resources, acceptable performance in terms of packet loss can be achieved for reasonable hardware resources with an appropriate design of the time/wavelength scheduling algorithms. Depending on the switching units (slots or bursts), an adapted scheduling algorithm needs to be deployed to exploit the bandwidth and buffer resources most efficiently.     

Performance Evaluation of Single-Wavelength Fiber Delay Line Buffer With Finite Waiting Places

The performance of single-wavelength fiber delay line buffer with finite waiting places is evaluated in this paper. For Poisson arriving packets with arbitrarily distributed lengths, the generating function of delay time distribution can be derived from the quantized delay buffer model. Then queue length distributions, loss probability, and other important performance measures can be figured out. Specifically, two important cases of negative-exponentially distributed packet lengths and fixed packet lengths are considered and compared. The accuracy of the proposed approach is verified through simulation. It is also observed that the buffer system performs more effectively for the fixed-length packets.     

A Quantized Delay Buffer Model for Single-Wavelength Fiber Delay Line Buffer

The fiber delay line (FDL) buffer is widely used in optical packet switching networks for contention solution. In this paper, a quantized delay buffer model is proposed to analyze the performance of the single-wavelength FDL buffer. Considering the delay quantization in the FDLs, the delay time and the waiting time of the packet are discussed. Without specific assumptions of the packet arrival process and length distribution, the model presents a generic approach to study the delay time distribution and modify the integral equation for the waiting time distribution. Analytic and exact results of the two aforementioned distributions can be obtained without any approximation. The accuracy of the model is validated through simulation.     

时隙可变长分组缓存调度算法

提出了一种采用时隙处理光分组竞争冲突的基于光纤延迟线的光分组交换缓存算法——时隙可变长分组缓存调度算法SVPB(slotted variable-length-packet-capable buffer)。该算法根据先到先服务的排队原则,通过对到来的光分组进行时间轴分段处理,解决了FDLs作为缓存器的不足。从仿真结果得到,在网络负载较高时所提出的调度算法SVPB比已有的调度算法分组丢失率有明显的降低。     

SLOB: a switch with large optical buffers for packet switching

Recently, optical packet switch architectures, composed of devices such as optical switches, fiber delay lines, and passive couplers, have been proposed to overcome the electromagnetic interference (EMI), pinout and interconnection problems that would be encountered in future large electronic switch cores. However, attaining the buffer size (buffer depth) in optical packet switches required in practice is a major problem; in this paper, a new solution is presented. An architectural concept is discussed and justified mathematically that relies on cascading many small switches to form a bigger switch with a larger buffer depth. The number of cascaded switches is proportional to the logarithm of the buffer depth, providing an economical and feasible hardware solution. Packet loss performance, control and buffer dimensioning are considered. The optical performance is also modeled, demonstrating the feasibility of buffer depths of several thousand, as required for bursty traffic     

Multiple-Input-Buffer and Shared-Buffer Architectures for Optical Packet- and Burst-Switching Networks

We present an architecture for implementing optical buffers, based on the feed-forward-buffer concept, that can truly emulate input queuing and accommodate asynchronous packet and burst operation. The architecture uses wavelength converters and fixed-length delay lines that are combined to form either a multiple-input buffer or a shared buffer. Both architectures are modular, allowing the expansion of the buffer at a cost that grows logarithmically with the buffer depth, where the cost is measured in terms of the number of switching elements, and wavelength converters are employed. The architectural design also provides a tradeoff between the number of wavelength converters and their tunability. The buffer architectures proposed are complemented with scheduling algorithms that can guarantee lossless communication and are evaluated using physical-layer simulations to obtain their performance in terms of bit-error rate and achievable buffer size.     

COD: alternative architectures for high speed packet switching

Architectures for packet switches are approaching the limit of electronic switching speed. This raises the question of how best to utilize advances in photonic technology to enable higher speeds. The authors introduce cascaded optical delay line (COD) architectures. The COD architectures utilize an extremely simple distributed electronic control algorithm to configure the states of 2×2 photonic switches and use optical fiber delay lines to temporarily buffer packets if necessary. The simplicity of the architectures may also make them suitable for “lightweight” all-electronic implementations. For optical implementations, the number of 2×2 photonic switches used is a significant factor determining cost. The authors present a “baseline” architecture for a 2×2 buffered packet switch that is work conserving and has the first-in, first-out (FIFO) property. If the arrival processes are independent and without memory, the maximum utilization factor is ρ, and the maximum acceptable packet loss probability is ϵ, then the required number of 2×2 photonic switches is O(log(ϵ)/log(γ)), where γ=ρ²/(ρ²+4-4ρ). If one modifies the baseline architecture by changing the delay line lengths then the system is no longer work conserving and loses the FIFO property, but the required number of 2×2 photonic switches is reduced to O(log[log(ϵ)/log(γ)]). The required number of 2×2 photonic switches is essentially insensitive to the distribution of packet arrivals, but long delay lines are required for bursty traffic     

Exploitation of DWDM for optical packet switching with quality ofservice guarantees

This paper addresses the problem of building optical packet switches that are able to effectively cope with variable length packet traffic and quality of service management, therefore able to support IP traffic. The paper aims at showing that the availability of dense wavelength division multiplexing is crucial. By suitably exploiting the wavelength dimension a multistage fiber delay line buffer can be implemented, with fine granularity and long delay with an architecture of limited complexity. This is necessary to fulfill the buffering requirements of variable length packets. Furthermore, the wavelength domain is proved to be more effective than the time domain to manage different levels of quality of service. Algorithms are presented that are peculiarly designed for this environment showing that they can effectively differentiate the packet loss probability between three priority classes     

Performance of two-stage shared fiber delay line optical packet switch under bursty traffic

Packet contention is a major issue in an optical packet switching network. It is not a trivial task to resolve contention due to lack of optical RAM technology. This article proposes a two-stage shared fiber delay line (FDL) optical packet switch for contention resolution. In this article, shared FDLs are used to buffer optical packets, in which a pool of buffer memory is shared among all switch output ports. Most of the existing optical buffering schemes are output-based which require a huge number of FDLs as well as a larger switch size that incur extra implementation cost. However, a shared buffering approach is considered in this article in order to reduce implementation cost. In this article, FDLs are implemented in two stages using an extremely simple auxiliary switch. The proposed switch architecture leads to more efficient use of buffer space. The superiority of the proposed switch architecture has been established by means of extensive simulations. The performance of the proposed switch is investigated under bursty traffic. Simulation result shows that the proposed switch can achieve satisfactory performance at the price of a reasonable amount of FDLs. Moreover, the significance of the proposed switch is confirmed by simulation.     

一种新颖的全光分组交换节点结构及其性能分析

本文提出了一种共享波长转换器和光纤延迟线的全光分组交换结构,与传统的设计方法和实验报道相比,该结构提供了更灵活的冲突解决措施.为了获得与在交换系统输入级分别为每个波长信道提供波长转换器相等价的性能,本文给出了交换结构最多所需的转换器数量.仿真结果表明,本文结构是兼顾交换系统体积、成本和性能等三方面较理想的折衷方案.研究还表明,光纤数与每纤的波长数量之积愈大,本文结构所节约的转换器和延迟线数量将愈加可观.     

A new wavelength-routed photonic packet buffer combining travelingdelay lines with delay-line loops

We present a new wavelength-routed photonic packet buffer that combines traveling delay lines with delay-line loops. The new packet buffer can effectively capitalize on the simplicity of traveling delay lines and the flexibility of delay-line loops. Three different packet buffering and scheduling techniques are investigated. The effectiveness of the new packet buffer is evaluated by computer simulation using a random traffic model. The simulation results show that the new packet buffer, in conjunction with the buffering and scheduling techniques, can efficiently make use of buffering spaces and, hence, substantially reduce the packet-loss probability by several orders of magnitude