小间距红外探测器读出电路铟凸点制备技术

介绍了一种用于10 μm小间距碲镉汞探测器铟凸点的制备工艺。新工艺有别于常规的剥离法,采用离子刻蚀手段对金属铟进行精确刻蚀,从而制备出高度大于6 μm且非均匀性小于±5 %的10 μm小间距红外探测器读出电路铟凸点,解决了传统工艺制备小间距铟凸点时高度不够且差异过大、易相互粘连等问题,大幅度提高了小间距红外探测器在互连工艺段的成功率。     

10 μm小间距红外探测器的铟柱生长研究

在10 μm小间距的条件下进行红外探测器的铟柱生长工艺,会得到铟柱高度不足的结果;本文针对这种情况,开展了小间距的铟柱生长研究,比较了在不同基片温度和蒸发速率条件下的铟柱高度,并分析了试验结果,得到了最优的生长工艺条件。     

铟凸点对倒装互连影响的研究

制作了2种形式的铟凸点:即直接蒸发沉积的铟柱和将铟柱回流得到的铟球.分别讨论了铟柱和铟球对倒装互连的影响,着重讨论了铟球和铟柱分别和芯片倒装互连后的剪切强度,结果发现在互连未回流的状态下铟球的剪切强度是铟柱的1.5倍,回流后铟球的剪切强度是铟柱的2.8倍.此外,分析讨论了长时间放置在空气中的铟球对倒装互连的影响,结果发现长时间放置在空气中的铟球和芯片互连后,器件的电学与机械连通性能会受到很大的影响.     

铟凸点回流时的异常现象的研究

利用湿法回流缩球的技术,使铟柱回流成铟球。在研究中心距为30?m、面阵为320×256的读出电路在回流缩球的过程中遇到了3种异常现象,即铟球体积异常、铟球桥接和铟球偏离中心位置的现象。详细地介绍了这3种现象产生的过程及背景,分析了产生这3种现象的机理以及对器件性能和倒装互连的影响,并提出了相应的解决措施。     

织构对铟凸点剪切强度的影响

制作了2种形式的铟凸点：即直接蒸发沉积的铟柱和将铟柱回流得到的铟球。同时对比了铟柱和铟球2种凸点的剪切强度，测试结果表明铟球剪切强度为5.6MPa，铟柱的剪切强度为1.9MPa，前者约为后者的2.9倍。对铟凸点微观结构的X光衍射分析发现：铟柱剪切强度低是织构弱化所致；铟球剪切强度高是由于回流破坏了铟柱的理想（101）丝织构模式，从而提高了铟球的剪切强度。     

电镀法铟凸点制备技术以及可靠性研究

铟凸点阵列通常被用于焦平面阵列与硅的读出电路间的倒装互连中。铟凸点制备技术是焦平面探测器制备的关键技术之一。本文阐述了一种基于电镀的铟凸点制备工艺流程;基于此流程,实验中成功制备出间距为100um,UBM直径为40um的16*16的焊球阵列。同时,实验中利用XRD技术对Ti/Pt对铟的阻挡性做出了研究,结果表明,Ti/Pt (300Å/200Å)在室温和200°C的温度下对铟均具有良好的阻挡性能。利用剪切力实验对铟凸点的可靠性做出了研究,实验结果表明,经过一次回流后,铟凸点的剪切有极大的变化,但之后增加回流次数,其剪切力变化不大,此现象可能与电镀铟内部的织构有关.本文也讨论了铟凸点的倒装工艺。     

小像元10μm中心距红外焦平面读出电路设计

研制出一款小像元10μm中心距红外焦平面探测器CMOS(complementary metal oxide semiconductor)读出电路ROIC(read out integrated circuit).读出电路设计包括积分后读出(integration then reading,ITR)和积分同时读出(int...     

10 μm间距红外探测器铟柱制备研究

小间距红外探测器目前已成为红外探测器技术发展的一个重要方向.用于连接探测器芯片与读出电路芯片的铟柱的制备工艺水平成为影响器件性能的一个重要因素.介绍了一种10μm间距红外探测器铟柱的制备工艺.新工艺采用多次铟柱生长结合离子刻蚀的手段,最终剥离和制备出高度为8 μm、非均匀性小于5％的10μm间距红外探测器读出电路铟柱,...     

7.5μm像元间距红外探测器三维电极的制备与应用

采用现有读出电路电极生长设备和直写式光刻设备开发了三维电极的制备工艺。在制备过程中,首先在读出电路表面制备三维电极,在碲镉汞芯片端生长铟饼,然后通过倒装互连工艺可以实现7.5μm像元间距的1k×1k碲镉汞芯片与读出电路的互连。可变参数包括金属生长角度、生长速率、生长厚度以及金属种类等。经研究发现,通过该工艺制备的7.5μm像元间距的三维电极高度可达到3.8μm,高度非均匀性小于3%,可以经受7.6×10^-5 N的压力。三维电极的应用,降低了倒装互连工艺对HgCdTe芯片平坦度和互连设备精度的要求,大幅提高了7.5μm像元间距红外探测器的互连成品率。     

Electroplated indium bump arrays and the bonding reliability

A novel electroplating indium bumping process is described,as a result of which indium bump arrays with a pitch of 100μm and a diameter of 40μm were successfully prepared.UBM(under bump metallization) for indium bumping was investigated with an XRD technique.The experimental results indicate that Ti/Pt(300(?)/200(?)) has an excellent barrier effect both at room temperature and at 200℃.The bonding reliability of the indium bumps was evaluated by a shear test.Results show that the shear strength of the ind...     

Characterization of bump arrays at RF/microwave frequencies

A systematic procedure for the characterization of complex bump configurations at RF and microwave frequencies, is presented. Beginning with simple arrangements—single- and two-coupled bumps—full-wave electromagnetic (EM) field analysis, circuit simulations and RF measurements were used for the development and validation of their respective equivalent circuit models. These models were then extended to characterize three-coupled bumps, both in linear and triangular configurations. Finally, a combination of all the electrical parameters obtained from these simple bump configurations was used to characterize a complete bump array, taking into consideration that for pitches used in most high-speed packages, EM coupling between a bump and its “next but one” neighbor can be neglected.     

Solder bump reliability-issues on bump layout

The reliability of solder bumps in a typical under-filled flip chip package is calculated three-dimensionally (3-D) using the finite element method and a viscoplastic material model for the solder. Simulations are performed with varying bump placement, underfill coverage and board size. The average plastic work in a bump is used to compare the loading and bump reliability of different geometries. The results show possible improvements over the traditional bump placement by changing the geometry of the interconnects on the flip chip package. Three changes that improve reliability are discussed in detail: the redistribution of bump rows, the reduction of board size and the inclusion of heat transfer bumps.     

Indium bump array fabrication on small CMOS circuit for flip-chip bonding

We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator.A chip holder with a via hole is used to coat the photoresist for indium bump lift-off.The 1000μm-wide photoresist edge bead around the circuit chip can be reduced to less than 500μm,which ensures the integrity of the indium bump array.64×64 indium arrays with 20μm-high,30μm-diameter bumps are successfully formed on a 5×6.5 mm~2 CMOS chip.     

小片CMOS驱动电路的倒装焊In柱阵列沉积

本文研究了在用于GaAs/AlGaAs多量子阱空间光调制器驱动电路小片芯片上进行In柱阵列沉积的方法。使用了带有中央通孔的甩胶套进行甩胶,可以将驱动电路小片上1000um宽的胶边减小至500um,有效保证了沉积In柱阵列的完整性。使用此方法,64x64,20um高,30um直径的In柱阵列能够完整沉积在5mmx6.5mm的CMOS驱动电路上。     

The design of small slot arrays

The differences in mutual coupling for a central slot and a peripheral slot cannot be ignored in small arrays if good patterns and impedance are to be obtained. A theory has been developed whereby the length and offset of every slot in the array can be determined, in the presence of mutual coupling, for a specified aperture distribution and impedance match. The theory enlarges on Stevenson's method, and uses a modified form of Booker's relation based on Babinet's principle to treat nonresonant longitudinal shunt slots in the broad wall of a rectangular waveguide. A general relation between slot voltage and mode voltage is developed, and then formulas are derived for the active, self-, and mutual admittances among slots. These formulas result in a design procedure. Analogous treatments of inclined series slots in rectangular guide and of strip-line-fed slots are possible. Comparison between various experiments and the theory is presented. Tests of the theory include the resonant length of a zero offset slot, resonant conductance versus offset and resonant conductance versus frequency for a single slot, and self- and mutual admittances for two staggered slots. The design and performance of a two-by-four longitudinal shunt slot array is also described.     

大规模制备定向排列的碳纳米管阵列

采用一种无模板的化学气相沉积法，在石英衬底上制备了大面积，高定向性、自支撑的碳纳米管阵列。二甲苯和二茂铁分别作为碳源和催化剂，连续进给到反应装置中，在一定温度条件下，碳纳米管自组织生成垂直于衬底方向的定向阵列。这种方法可以获得很高的生长速度，其最大长度可以达到几个毫米。拉曼光谱和高分辨透射电镜检测显示这种方法制备的碳纳米管具有较高的纯度和石墨化程度。     

大规模制备定向排列的碳纳米管阵列

采用一种无模板的化学气相沉积法 ,在石英衬底上制备了大面积 ,高定向性、自支撑的碳纳米管阵列。二甲苯和二茂铁分别作为碳源和催化剂 ,连续进给到反应装置中 ,在一定温度条件下 ,碳纳米管自组织生成垂直于衬底方向的定向阵列。这种方法可以获得很高的生长速度 ,其最大长度可以达到几个毫米。拉曼光谱和高分辨透射电镜检测显示这种方法制备的碳纳米管具有较高的纯度和石墨化程度